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di: play 1080i timing always print di err[1/1]

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PD#SWPL-5807

Problem:
1080i always print di err,modify di pre idle register
define are wrong

Solution:
1.modify register define according g12a

Verify:
g12a

Change-Id: I13400d8b18e0e85894ba8d10afc0ae119874aab4
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>

Conflicts:
	drivers/amlogic/media/deinterlace/deinterlace.c
This commit is contained in:
Yong Qin
2019-03-13 14:05:34 +08:00
committed by Luke Go
parent a6a9f9a437
commit 616fcbb18c
3 changed files with 14 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/amlogic/media/deinterlace/deinterlace.c
View File

@@ -129,7 +129,7 @@ static di_dev_t *de_devp;
static dev_t di_devno;
static struct class *di_clsp;
static const char version_s[] = "2019-02-27a";
static const char version_s[] = "2019-03-14a";
static int bypass_state = 1;
static int bypass_all;

20
drivers/amlogic/media/deinterlace/deinterlace_hw.c
View File

@@ -3403,12 +3403,12 @@ bool di_pre_idle(void)
{
bool ret = false;
if (is_meson_tl1_cpu()) {
if ((RDMA_RD(VPU_ARB_DBG_STAT_L1C1_TL1) &
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
if ((RDMA_RD(DI_ARB_DBG_STAT_L1C1) &
PRE_ID_MASK_TL1) == PRE_ID_MASK_TL1)
ret = true;
} else {
if ((RDMA_RD(VPU_ARB_DBG_STAT_L1C1) &
if ((RDMA_RD(DI_ARB_DBG_STAT_L1C1_OLD) &
PRE_ID_MASK) == PRE_ID_MASK)
ret = true;
}
@@ -3425,18 +3425,18 @@ void di_arb_sw(bool on)
u32 WRARB_onval;
u32 WRARB_offval;
if (is_meson_tl1_cpu()) {
REG_VPU_WRARB_REQEN_SLV_L1C1 = VPU_WRARB_REQEN_SLV_L1C1_TL1;
REG_VPU_RDARB_REQEN_SLV_L1C1 = VPU_RDARB_REQEN_SLV_L1C1_TL1;
REG_VPU_ARB_DBG_STAT_L1C1 = VPU_ARB_DBG_STAT_L1C1_TL1;
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
REG_VPU_WRARB_REQEN_SLV_L1C1 = DI_WRARB_REQEN_SLV_L1C1;
REG_VPU_RDARB_REQEN_SLV_L1C1 = DI_RDARB_REQEN_SLV_L1C1;
REG_VPU_ARB_DBG_STAT_L1C1 = DI_ARB_DBG_STAT_L1C1;
if (on)
WRARB_onval = 0x3f;
else
WRARB_offval = 0x3e;
} else {
REG_VPU_WRARB_REQEN_SLV_L1C1 = VPU_WRARB_REQEN_SLV_L1C1;
REG_VPU_RDARB_REQEN_SLV_L1C1 = VPU_RDARB_REQEN_SLV_L1C1;
REG_VPU_ARB_DBG_STAT_L1C1 = VPU_ARB_DBG_STAT_L1C1;
REG_VPU_WRARB_REQEN_SLV_L1C1 = DI_WRARB_REQEN_SLV_L1C1_OLD;
REG_VPU_RDARB_REQEN_SLV_L1C1 = DI_RDARB_REQEN_SLV_L1C1_OLD;
REG_VPU_ARB_DBG_STAT_L1C1 = DI_ARB_DBG_STAT_L1C1_OLD;
if (on)
WRARB_onval = 0x3f;
else

11
drivers/amlogic/media/deinterlace/register.h
View File

@@ -44,14 +44,9 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
#define HHI_VPU_CLKB_CNTL 0x83
#define VPU_WRARB_REQEN_SLV_L1C1 0x2795
#define VPU_RDARB_REQEN_SLV_L1C1 0x2791
#define VPU_ARB_DBG_STAT_L1C1 0x27b4
#define VPU_WRARB_REQEN_SLV_L1C1_TL1 0x2055
#define VPU_RDARB_REQEN_SLV_L1C1_TL1 0x2051
#define VPU_ARB_DBG_STAT_L1C1_TL1 0x205a
#define DI_WRARB_REQEN_SLV_L1C1_OLD 0x2795
#define DI_RDARB_REQEN_SLV_L1C1_OLD 0x2791
#define DI_ARB_DBG_STAT_L1C1_OLD 0x27b4
#define VIUB_SW_RESET 0x2001
#define VIUB_SW_RESET0 0x2002