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di: enable read mif go field reset default

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PD#165701: di: enable read mif go field reset default

1.enable di pre and post read mif go field reset
2.enable vd1 and vd2 read mif go field reset

Change-Id: I74db04ed345f348a805634b3e97f381cfb532963
Signed-off-by: Dezhi Kong <dezhi.kong@amlogic.com>
This commit is contained in:
Dezhi Kong
2018-05-30 15:43:05 +08:00
committed by Jianxin Pan
parent aecabfb3d0
commit 61c81bc3d5
2 changed files with 8 additions and 6 deletions
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12
drivers/amlogic/media/deinterlace/deinterlace_hw.c
View File

@@ -1095,7 +1095,7 @@ static void set_di_inp_mif(struct DI_MIF_s *mif, int urgent, int hold_line)
/* ---------------------- */
/* General register */
/* ---------------------- */
reset_on_gofield = 0;
reset_on_gofield = 1;/* default enable according to vlsi */
RDMA_WR(DI_INP_GEN_REG, (reset_on_gofield << 29) |
(urgent << 28) |/* chroma urgent bit */
(urgent << 27) |/* luma urgent bit. */
@@ -1305,7 +1305,7 @@ static void set_di_mem_mif(struct DI_MIF_s *mif, int urgent, int hold_line)
/* ---------------------- */
/* General register */
/* ---------------------- */
reset_on_gofield = 0;
reset_on_gofield = 1;/* default enable according to vlsi */
RDMA_WR(DI_MEM_GEN_REG, (reset_on_gofield << 29) |
/* reset on go field */
(urgent << 28) | /* urgent bit. */
@@ -1519,7 +1519,7 @@ static void set_di_if2_mif(struct DI_MIF_s *mif, int urgent,
/* General register */
/* ---------------------- */
DI_VSYNC_WR_MPEG_REG(DI_IF2_GEN_REG, (0 << 29) | /* reset on go field */
DI_VSYNC_WR_MPEG_REG(DI_IF2_GEN_REG, (1 << 29) | /* reset on go field */
(urgent << 28) |/* urgent */
(urgent << 27) |/* luma urgent */
(1 << 25)|/* no dummy data. */
@@ -1619,7 +1619,7 @@ static void set_di_if1_mif(struct DI_MIF_s *mif, int urgent,
/* General register */
/* ---------------------- */
DI_VSYNC_WR_MPEG_REG(DI_IF1_GEN_REG, (0 << 29) | /* reset on go field */
DI_VSYNC_WR_MPEG_REG(DI_IF1_GEN_REG, (1 << 29) | /* reset on go field */
(urgent << 28) |/* urgent */
(urgent << 27) |/* luma urgent */
(1 << 25)|/* no dummy data. */
@@ -1742,7 +1742,7 @@ static void set_di_chan2_mif(struct DI_MIF_s *mif, int urgent, int hold_line)
/* ---------------------- */
/* General register */
/* ---------------------- */
reset_on_gofield = 0;
reset_on_gofield = 1;/* default enable according to vlsi */
RDMA_WR(DI_CHAN2_GEN_REG, (reset_on_gofield << 29) |
(urgent << 28) | /* urgent */
(urgent << 27) | /* luma urgent */
@@ -1979,7 +1979,7 @@ static void set_di_if0_mif_g12(struct DI_MIF_s *mif, int urgent, int hold_line,
mif->set_separate_en ? 0 : (mif->video_mode ? 2 : 1);
demux_mode = mif->video_mode;
DI_VSYNC_WR_MPEG_REG(DI_IF0_GEN_REG,
(0 << 29) | /* reset on go field */
(1 << 29) | /* reset on go field */
(urgent << 28) | /* urgent */
(urgent << 27) | /* luma urgent */
(1 << 25) | /* no dummy data. */

2
drivers/amlogic/media/video_sink/video.c
View File

@@ -2772,6 +2772,8 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
if (frame_par->hscale_skip_count)
r |= VDIF_CHROMA_HZ_AVG | VDIF_LUMA_HZ_AVG;
/*enable go field reset default according to vlsi*/
r |= VDIF_RESET_ON_GO_FIELD;
VSYNC_WR_MPEG_REG(VD1_IF0_GEN_REG + cur_dev->viu_off, r);
if (!vf_with_el)
VSYNC_WR_MPEG_REG(