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UPSTREAM: usb: dwc2: reset dwc2 core before dwc2_get_hwparams()
We initiate dwc2 usb controller in BIOS, dwc2_core_reset() should
be called before dwc2_get_hwparams() to reset core registers to
default value. Without this the FIFO setting might be incorrect
because calculating FIFO size need power-on value of
GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers.
This patch could avoid warnning massage like in rk3288 platform:
[ 2.074764] dwc2 ff580000.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.
Change-Id: Iab346c005c9f3ea940f4070f3e433e0c7ea89087
Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit cebfdbf329)
This commit is contained in:
@@ -481,7 +481,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
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* Do core a soft reset of the core. Be careful with this because it
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* resets all the internal state machines of the core.
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*/
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static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
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int dwc2_core_reset(struct dwc2_hsotg *hsotg)
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{
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u32 greset;
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int count = 0;
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@@ -891,6 +891,7 @@ enum dwc2_halt_status {
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* The following functions support initialization of the core driver component
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* and the DWC_otg controller
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*/
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extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
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extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
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extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
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extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
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@@ -419,6 +419,12 @@ static int dwc2_driver_probe(struct platform_device *dev)
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if (retval)
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return retval;
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/*
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* Reset before dwc2_get_hwparams() then it could get power-on real
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* reset value form registers.
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*/
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dwc2_core_reset(hsotg);
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/* Detect config values from hardware */
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retval = dwc2_get_hwparams(hsotg);
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if (retval)
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