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ARM: rockchip: l2 and cpu_axi_bus DT add rockchip prefix
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@@ -61,9 +61,9 @@
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cache-level = <2>;
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arm,tag-latency = <1 1 1>;
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arm,data-latency = <2 3 1>;
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prefetch-ctrl = <0x70000003>;
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rockchip,prefetch-ctrl = <0x70000003>;
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/* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
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power-ctrl = <0x3>;
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rockchip,power-ctrl = <0x3>;
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/*
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(0x1 << 0) | // Full line of write zero behavior Enabled
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(0x1 << 25) | // Round-robin replacement
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@@ -71,7 +71,7 @@
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(0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
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(0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
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*/
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aux-ctrl = <0x72000001 (~0x72000001)>;
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rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
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};
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cpu_axi_bus: cpu_axi_bus@10128000 {
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@@ -79,51 +79,51 @@
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reg = <0x10128000 0x8000>;
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qos {
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dmac {
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offset = <0x1000>;
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priority = <0 0>;
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rockchip,offset = <0x1000>;
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rockchip,priority = <0 0>;
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};
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cpu0 {
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offset = <0x2000>;
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priority = <0 0>;
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rockchip,offset = <0x2000>;
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rockchip,priority = <0 0>;
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};
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cpu1r {
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offset = <0x2080>;
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priority = <0 0>;
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rockchip,offset = <0x2080>;
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rockchip,priority = <0 0>;
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};
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cpu1w {
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offset = <0x2100>;
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priority = <0 0>;
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rockchip,offset = <0x2100>;
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rockchip,priority = <0 0>;
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};
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peri {
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offset = <0x4000>;
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priority = <2 2>;
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rockchip,offset = <0x4000>;
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rockchip,priority = <2 2>;
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};
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gpu {
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offset = <0x5000>;
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priority = <2 1>;
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rockchip,offset = <0x5000>;
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rockchip,priority = <2 1>;
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};
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vpu {
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offset = <0x6000>;
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rockchip,offset = <0x6000>;
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};
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vop0 {
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offset = <0x7000>;
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priority = <3 3>;
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rockchip,offset = <0x7000>;
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rockchip,priority = <3 3>;
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};
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cif0 {
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offset = <0x7080>;
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rockchip,offset = <0x7080>;
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};
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ipp {
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offset = <0x7100>;
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rockchip,offset = <0x7100>;
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};
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vop1 {
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offset = <0x7180>;
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priority = <3 3>;
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rockchip,offset = <0x7180>;
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rockchip,priority = <3 3>;
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};
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cif1 {
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offset = <0x7200>;
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rockchip,offset = <0x7200>;
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};
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rga {
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offset = <0x7280>;
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rockchip,offset = <0x7280>;
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};
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};
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};
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@@ -36,23 +36,23 @@ static int __init rockchip_cpu_axi_init(void)
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if (np) {
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for_each_child_of_node(np, cp) {
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u32 offset, priority[2], mode, bandwidth, saturation;
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if (of_property_read_u32(cp, "offset", &offset))
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if (of_property_read_u32(cp, "rockchip,offset", &offset))
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continue;
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pr_debug("qos: %s offset %x\n", cp->name, offset);
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cbase = base + offset;
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if (!of_property_read_u32_array(cp, "priority", priority, ARRAY_SIZE(priority))) {
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if (!of_property_read_u32_array(cp, "rockchip,priority", priority, ARRAY_SIZE(priority))) {
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CPU_AXI_SET_QOS_PRIORITY(priority[0], priority[1], cbase);
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pr_debug("qos: %s priority %x %x\n", cp->name, priority[0], priority[1]);
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}
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if (!of_property_read_u32(cp, "mode", &mode)) {
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if (!of_property_read_u32(cp, "rockchip,mode", &mode)) {
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CPU_AXI_SET_QOS_MODE(mode, cbase);
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pr_debug("qos: %s mode %x\n", cp->name, mode);
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}
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if (!of_property_read_u32(cp, "bandwidth", &bandwidth)) {
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if (!of_property_read_u32(cp, "rockchip,bandwidth", &bandwidth)) {
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CPU_AXI_SET_QOS_BANDWIDTH(bandwidth, cbase);
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pr_debug("qos: %s bandwidth %x\n", cp->name, bandwidth);
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}
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if (!of_property_read_u32(cp, "saturation", &saturation)) {
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if (!of_property_read_u32(cp, "rockchip,saturation", &saturation)) {
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CPU_AXI_SET_QOS_SATURATION(saturation, cbase);
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pr_debug("qos: %s saturation %x\n", cp->name, saturation);
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}
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@@ -87,13 +87,13 @@ static int __init rockchip_pl330_l2_cache_init(void)
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if (!base)
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return -EINVAL;
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if (!of_property_read_u32(np, "prefetch-ctrl", &prefetch)) {
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if (!of_property_read_u32(np, "rockchip,prefetch-ctrl", &prefetch)) {
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/* L2X0 Prefetch Control */
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writel_relaxed(prefetch, base + L2X0_PREFETCH_CTRL);
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pr_debug("l2c: prefetch %x\n", prefetch);
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}
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if (!of_property_read_u32(np, "power-ctrl", &power)) {
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if (!of_property_read_u32(np, "rockchip,power-ctrl", &power)) {
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/* L2X0 Power Control */
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writel_relaxed(power, base + L2X0_POWER_CTRL);
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pr_debug("l2c: power %x\n", power);
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@@ -101,7 +101,7 @@ static int __init rockchip_pl330_l2_cache_init(void)
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iounmap(base);
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of_property_read_u32_array(np, "aux-ctrl", aux, ARRAY_SIZE(aux));
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of_property_read_u32_array(np, "rockchip,aux-ctrl", aux, ARRAY_SIZE(aux));
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pr_debug("l2c: aux %08x mask %08x\n", aux[0], aux[1]);
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l2x0_of_init(aux[0], aux[1]);
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