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arm64: dts: rockchip: add rk3358 evb for linux
Signed-off-by: Caesar Wang <wxt@rock-chips.com> Change-Id: I64fd77f17c4df93dc1ba14b19a054ec551500ba8
This commit is contained in:
Caesar Wang
@@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3358-evb-ddr3-v10-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb
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15
arch/arm64/boot/dts/rockchip/rk3358-evb-ddr3-v10-linux.dts
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15
arch/arm64/boot/dts/rockchip/rk3358-evb-ddr3-v10-linux.dts
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@@ -0,0 +1,15 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "rk3358-evb-ddr3.dtsi"
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#include "rk3358-linux.dtsi"
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/ {
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model = "Rockchip linux RK3358 EVB DDR3 board";
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compatible = "rockchip,rk3358-evb-ddr3-v10-linux", "rockchip,px30", "rockchip,rk3358";
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};
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1089
arch/arm64/boot/dts/rockchip/rk3358-evb-ddr3.dtsi
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1089
arch/arm64/boot/dts/rockchip/rk3358-evb-ddr3.dtsi
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File diff suppressed because it is too large
Load Diff
49
arch/arm64/boot/dts/rockchip/rk3358-linux.dtsi
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49
arch/arm64/boot/dts/rockchip/rk3358-linux.dtsi
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@@ -0,0 +1,49 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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*/
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/ {
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compatible = "rockchip,linux", "rockchip,rk3358", "rockchip,px30";
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootwait";
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};
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fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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rockchip,serial-id = <2>;
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rockchip,wake-irq = <0>;
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/* If enable uart uses irq instead of fiq */
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rockchip,irq-mode-enable = <0>;
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rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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status = "okay";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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drm_logo: drm-logo@00000000 {
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compatible = "rockchip,drm-logo";
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reg = <0x0 0x0 0x0 0x0>;
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};
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};
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};
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&cpu0_opp_table {
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rockchip,avs = <1>;
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};
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&rng {
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status = "okay";
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};
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&video_phy {
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status = "okay";
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};
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122
arch/arm64/boot/dts/rockchip/rk3358.dtsi
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122
arch/arm64/boot/dts/rockchip/rk3358.dtsi
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@@ -0,0 +1,122 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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*/
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#include "px30.dtsi"
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&cpu0_opp_table {
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/delete-node/ opp-1200000000;
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/delete-node/ opp-1248000000;
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/delete-node/ opp-1296000000;
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/delete-node/ opp-1416000000;
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/delete-node/ opp-1512000000;
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};
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&cru {
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assigned-clocks = <&cru PLL_NPLL>;
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assigned-clock-rates = <1040000000>;
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};
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&display_subsystem {
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status = "disabled";
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ports = <&vopb_out>, <&vopl_out>;
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logo-memory-region = <&drm_logo>;
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route {
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route_lvds: route-lvds {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopb_out_lvds>;
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};
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route_dsi: route-dsi {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopb_out_dsi>;
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};
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route_rgb: route-rgb {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopb_out_rgb>;
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};
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};
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};
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&gpu_opp_table {
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opp-520000000 {
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opp-hz = /bits/ 64 <520000000>;
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opp-microvolt = <1175000>;
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opp-microvolt-L0 = <1175000>;
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opp-microvolt-L1 = <1150000>;
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opp-microvolt-L2 = <1100000>;
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opp-microvolt-L3 = <1050000>;
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};
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};
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&rgb {
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phys = <&video_phy>;
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phy-names = "phy";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&lcdc_m1_rgb_pins>;
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pinctrl-1 = <&lcdc_m1_sleep_pins>;
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};
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&pinctrl {
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lcdc {
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lcdc_m1_rgb_pins: lcdc-m1-rgb-pins {
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rockchip,pins =
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<3 RK_PA0 1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */
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<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* LCDC_D0 */
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<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* LCDC_D2 */
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<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* LCDC_D6 */
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<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* LCDC_D7 */
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<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* LCDC_D9 */
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<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* LCDC_D12 */
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<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* LCDC_D13 */
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<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* LCDC_D14 */
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<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* LCDC_D15 */
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<3 RK_PC4 1 &pcfg_pull_none_8ma>, /* LCDC_D16 */
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<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* LCDC_D17 */
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<3 RK_PC6 1 &pcfg_pull_none_8ma>, /* LCDC_D18 */
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<3 RK_PC7 1 &pcfg_pull_none_8ma>, /* LCDC_D19 */
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<3 RK_PD0 1 &pcfg_pull_none_8ma>, /* LCDC_D20 */
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<3 RK_PD1 1 &pcfg_pull_none_8ma>, /* LCDC_D21 */
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<3 RK_PD2 1 &pcfg_pull_none_8ma>, /* LCDC_D22 */
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<3 RK_PD3 1 &pcfg_pull_none_8ma>; /* LCDC_D23 */
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};
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lcdc_m1_sleep_pins: lcdc-m1-sleep-pins {
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rockchip,pins =
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<3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */
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<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */
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<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */
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<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */
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<3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */
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<3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */
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<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
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<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
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<3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
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<3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
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<3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
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<3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
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<3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
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<3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
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<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
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<3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
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<3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
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<3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D23 */
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};
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};
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};
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