ODROID-COMMON: hdmitx: Add new hdmi resolutions of 2560x* and 3440x1440

In case of 2560x1600@60hz, unstable display operation may occur
with some specific monitors those pixel clock is under 300MHz.
So, default timing for 2560x1600p60hz is set as following.

Detailed mode: Clock 268.500 MHz, 641 mm x 401 mm
               2560 2608 2640 2720 ( 48  32  80)
               1600 1602 1608 1646 (  2   6  38)
               +hsync -vsync
               VertFreq: 59.972 Hz, HorFreq: 98.713 kHz

Change-Id: Iec9df8713211cf5e0dc7ba09f3dba2948e479b4f
This commit is contained in:
Joy Cho
2020-09-14 23:56:27 +09:00
committed by Chris
parent fda5d9b946
commit 62f248084b
7 changed files with 208 additions and 38 deletions

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@@ -2686,26 +2686,26 @@ static struct hdmi_format_para fmt_para_vesa_2560x1600p60_8x5 = {
.progress_mode = 1,
.scrambler_en = 0,
.tmds_clk_div40 = 0,
.tmds_clk = 348500,
.tmds_clk = 268000,
.timing = {
.pixel_freq = 348500,
.h_freq = 99458,
.v_freq = 59987,
.pixel_freq = 268000,
.h_freq = 98529,
.v_freq = 59859,
.vsync = 60,
.vsync_polarity = 1,
.hsync_polarity = 1,
.hsync_polarity = 0,
.h_active = 2560,
.h_total = 3504,
.h_blank = 944,
.h_front = 192,
.h_sync = 280,
.h_back = 472,
.h_total = 2720,
.h_blank = 160,
.h_front = 48,
.h_sync = 32,
.h_back = 80,
.v_active = 1600,
.v_total = 1658,
.v_blank = 58,
.v_front = 3,
.v_total = 1646,
.v_blank = 46,
.v_front = 2,
.v_sync = 6,
.v_back = 49,
.v_back = 38,
.v_sync_ln = 1,
},
.hdmitx_vinfo = {
@@ -2718,15 +2718,63 @@ static struct hdmi_format_para fmt_para_vesa_2560x1600p60_8x5 = {
.aspect_ratio_den = 5,
.sync_duration_num = 60,
.sync_duration_den = 1,
.video_clk = 348500000,
.htotal = 3504,
.vtotal = 1658,
.video_clk = 268000000,
.htotal = 2720,
.vtotal = 1646,
.fr_adj_type = VOUT_FR_ADJ_HDMI,
.viu_color_fmt = COLOR_FMT_YUV444,
.viu_mux = VIU_MUX_ENCP,
},
};
static struct hdmi_format_para fmt_para_vesa_3440x1440p60_43x18 = {
.vic = HDMIV_3440x1440p60hz,
.name = "3440x1440p60hz",
.sname = "3440x1440p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
.tmds_clk_div40 = 0,
.tmds_clk = 319750,
.timing = {
.pixel_freq = 319750,
.frac_freq = 319750,
.h_freq = 88819,
.v_freq = 60000,
.vsync_polarity = 0, /* -VSync */
.hsync_polarity = 1, /* +HSync */
.h_active = 3440,
.h_total = 3600,
.h_blank = 160,
.h_front = 48,
.h_sync = 32,
.h_back = 80,
.v_active = 1440,
.v_total = 1481,
.v_blank = 41,
.v_front = 3,
.v_sync = 10,
.v_back = 28,
.v_sync_ln = 1,
},
.hdmitx_vinfo = {
.name = "3440x1440p60hz",
.mode = VMODE_HDMI,
.width = 3440,
.height = 1440,
.field_height = 1440,
.aspect_ratio_num = 43,
.aspect_ratio_den = 19,
.sync_duration_num = 60,
.sync_duration_den = 1,
.video_clk = 319750000,
.htotal = 3600,
.vtotal = 1481,
.viu_color_fmt = COLOR_FMT_YUV444,
.viu_mux = VIU_MUX_ENCP,
},
};
static struct hdmi_format_para fmt_para_custombuilt = {
.vic = HDMI_CUSTOMBUILT,
.name = "custombuilt",
@@ -2852,6 +2900,7 @@ static struct hdmi_format_para *all_fmt_paras[] = {
&fmt_para_vesa_2160x1200p90_9x5,
&fmt_para_vesa_2560x1600p60_8x5,
&fmt_para_vesa_2560x1440p60_16x9,
&fmt_para_vesa_3440x1440p60_43x18,
&fmt_para_custombuilt,
&fmt_para_null_hdmi_fmt,
&fmt_para_non_hdmi_fmt,

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@@ -2572,7 +2572,6 @@ static struct dispmode_vic dispmode_vic_tab[] = {
{"2560x1080p60hz", HDMIV_2560x1080p60hz},
{"2560x1440p60hz", HDMIV_2560x1440p60hz},
{"2560x1600p60hz", HDMIV_2560x1600p60hz},
{"2560x1440p60hz", HDMIV_2560x1440p60hz},
{"3440x1440p60hz", HDMIV_3440x1440p60hz},
{"custombuilt", HDMI_CUSTOMBUILT},
};

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@@ -821,15 +821,15 @@ static struct hdmitx_vidpara hdmi_tx_video_params[] = {
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_2560x1440p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.VIC = HDMIV_3440x1440p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
.aspect_ratio = ASPECT_RATIO_SAME_AS_SOURCE,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_CUSTOMBUILT,

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@@ -1338,28 +1338,81 @@ static const struct reg_s tvregs_vesa_2160x1200p90hz[] = {
};
static const struct reg_s tvregs_vesa_2560x1600p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0xDAF,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x679,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x2F0,},
{P_ENCP_VIDEO_HAVON_END, 0xCEF,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x37,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x676,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x118,},
{P_ENCP_VIDEO_MAX_PXCNT, 0xA9F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x66D,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x50,},
{P_ENCP_VIDEO_HAVON_END, 0xA4F,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x26,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x665,},
{P_ENCP_VIDEO_HSO_BEGIN, 0,},
{P_ENCP_VIDEO_HSO_END, 0x20,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0}
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0},
};
static const struct reg_s tvregs_vesa_2560x1440p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0xA9F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x5C8,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x50,},
{P_ENCP_VIDEO_HAVON_END, 0xA4F,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x22,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x5C1,},
{P_ENCP_VIDEO_HSO_BEGIN, 0,},
{P_ENCP_VIDEO_HSO_END, 0x20,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x5,},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0},
};
static const struct reg_s tvregs_vesa_3440x1440p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 3599,},
{P_ENCP_VIDEO_MAX_LNCNT, 1480,},
{P_ENCP_VIDEO_HAVON_BEGIN, 80,},
{P_ENCP_VIDEO_HAVON_END, 3519,},
{P_ENCP_VIDEO_VAVON_BLINE, 28,},
{P_ENCP_VIDEO_VAVON_ELINE, 1467,},
{P_ENCP_VIDEO_HSO_BEGIN, 0,},
{P_ENCP_VIDEO_HSO_END, 32,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 10,},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0},
};
#if 0 /* TODO */
@@ -1505,6 +1558,8 @@ static struct vic_tvregs_set tvregsTab[] = {
{HDMIV_1920x1200p60hz, tvregs_vesa_1920x1200p60hz},
{HDMIV_2160x1200p90hz, tvregs_vesa_2160x1200p90hz},
{HDMIV_2560x1600p60hz, tvregs_vesa_2560x1600p60hz},
{HDMIV_2560x1440p60hz, tvregs_vesa_2560x1440p60hz},
{HDMIV_3440x1440p60hz, tvregs_vesa_3440x1440p60hz},
};
/*

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@@ -1728,6 +1728,54 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
SOF_LINES = hdmi_encp_timing->v_back;
TOTAL_FRAMES = 4;
break;
case HDMIV_2560x1600p60hz:
INTERLACE_MODE = 0U;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (2560*(1+PIXEL_REPEAT_HDMI));
ACTIVE_LINES = (1600/(1+INTERLACE_MODE));
LINES_F0 = 1646;
LINES_F1 = 1646;
FRONT_PORCH = 48;
HSYNC_PIXELS = 32;
BACK_PORCH = 80;
EOF_LINES = 2;
VSYNC_LINES = 3;
SOF_LINES = 19;
TOTAL_FRAMES = 4;
break;
case HDMIV_2560x1440p60hz:
INTERLACE_MODE = 0U;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (2560*(1+PIXEL_REPEAT_HDMI));
ACTIVE_LINES = (1440/(1+INTERLACE_MODE));
LINES_F0 = 1481;
LINES_F1 = 1481;
FRONT_PORCH = 48;
HSYNC_PIXELS = 32;
BACK_PORCH = 80;
EOF_LINES = 2;
VSYNC_LINES = 5;
SOF_LINES = 34;
TOTAL_FRAMES = 4;
break;
case HDMIV_3440x1440p60hz:
INTERLACE_MODE = 0U;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (3440*(1+PIXEL_REPEAT_HDMI));
ACTIVE_LINES = (1440/(1+INTERLACE_MODE));
LINES_F0 = 1481;
LINES_F1 = 1481;
FRONT_PORCH = 48;
HSYNC_PIXELS = 32;
BACK_PORCH = 80;
EOF_LINES = 3;
VSYNC_LINES = 10;
SOF_LINES = 28;
TOTAL_FRAMES = 4;
break;
case HDMI_CUSTOMBUILT:
custom_timing = get_custom_timing();
INTERLACE_MODE = 0U;

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@@ -889,7 +889,13 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
5371100, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMIV_2560x1600p60hz,
HDMI_VIC_END},
3485000, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
5370000, 2, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMIV_2560x1440p60hz,
HDMI_VIC_END},
4830000, 2, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMIV_3440x1440p60hz,
HDMI_VIC_END},
3197500, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMI_CUSTOMBUILT,
HDMI_VIC_END},
/* default 1080p60hz */

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@@ -225,6 +225,19 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
break;
case 5370000:
/* stability issue : 5370000 (0xdf) -> 5360000 (0xde) */
hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004de);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
break;
case 4897000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004cc);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0000d560);