Merge remote-tracking branch 'origin/develop-3.0-rk30' into develop-3.0

This commit is contained in:
黄涛
2012-03-25 15:55:20 +08:00
5 changed files with 19 additions and 14 deletions

3
arch/arm/configs/rk30_sdk_defconfig Normal file → Executable file
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@@ -285,7 +285,10 @@ CONFIG_HID_APPLE=y
CONFIG_HID_ELECOM=y
CONFIG_HID_MAGICMOUSE=y
CONFIG_HID_WACOM=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB20_HOST=y
CONFIG_USB20_OTG=y
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y

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@@ -429,7 +429,7 @@ typedef struct dwc_otg_core_params
* Note: The FPGA configuration supports a maximum of 12 host channels.
*/
int32_t host_channels;
#define dwc_param_host_channels_default 12
#define dwc_param_host_channels_default 16
/** The number of endpoints in addition to EP0 available for device
* mode operations.

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@@ -2012,6 +2012,9 @@ static __devinit int host20_driver_probe(struct platform_device *pdev)
cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_PHY, false);
cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_CONTROLLER, false);
#endif
#ifdef CONFIG_ARCH_RK30
*(unsigned int*)(USBGRF_UOC1_CON2+4) = ((1<<5)|((1<<5)<<16));
#endif
if (dwc_otg_device == 0)
{
dev_err(dev, "kmalloc of dwc_otg_device failed\n");

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@@ -1396,7 +1396,6 @@ void dwc_otg_hcd_free(struct usb_hcd *_hcd)
return;
}
#ifdef DEBUG
static void dump_urb_info(struct urb *_urb, char* _fn_name)
{
@@ -1511,17 +1510,6 @@ int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd,
return retval;
}
#endif
#if 1
/*
* Make sure the start of frame interrupt is enabled now that
* we know we should have queued data. The SOF interrupt
* handler automatically disables itself when idle to reduce
* the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
* for the disable
*/
dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0,
DWC_SOF_INTR_MASK);
#endif
#ifdef DEBUG
if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue");
@@ -1544,6 +1532,17 @@ int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd,
"Error status %d\n", retval);
dwc_otg_hcd_qtd_free(qtd);
}
#if 1
/*
* Make sure the start of frame interrupt is enabled now that
* we know we should have queued data. The SOF interrupt
* handler automatically disables itself when idle to reduce
* the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
* for the disable
*/
dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0,
DWC_SOF_INTR_MASK);
#endif
out:
return retval;

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@@ -1912,7 +1912,7 @@ int dwc_otg_pcd_init(struct device *dev)
pcd->vbus_status = 0;
pcd->phy_suspend = 0;
if(dwc_otg_is_device_mode(core_if))
mod_timer(&pcd->check_vbus_timer, jiffies+(HZ<<2)); // delay 16 S +(HZ<<4)
mod_timer(&pcd->check_vbus_timer, jiffies+(HZ<<4)); // delay 16 S
DWC_PRINT("%s pass,everest\n", __func__);
// dwc_otg_pcd_start_vbus_timer( pcd );
return 0;