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Merge remote-tracking branch 'origin/develop-3.0-rk30' into develop-3.0
This commit is contained in:
3
arch/arm/configs/rk30_sdk_defconfig
Normal file → Executable file
3
arch/arm/configs/rk30_sdk_defconfig
Normal file → Executable file
@@ -285,7 +285,10 @@ CONFIG_HID_APPLE=y
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CONFIG_HID_ELECOM=y
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CONFIG_HID_MAGICMOUSE=y
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CONFIG_HID_WACOM=y
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CONFIG_USB=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_GADGET=y
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CONFIG_USB20_HOST=y
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CONFIG_USB20_OTG=y
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CONFIG_MMC=y
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CONFIG_MMC_UNSAFE_RESUME=y
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@@ -429,7 +429,7 @@ typedef struct dwc_otg_core_params
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* Note: The FPGA configuration supports a maximum of 12 host channels.
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*/
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int32_t host_channels;
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#define dwc_param_host_channels_default 12
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#define dwc_param_host_channels_default 16
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/** The number of endpoints in addition to EP0 available for device
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* mode operations.
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@@ -2012,6 +2012,9 @@ static __devinit int host20_driver_probe(struct platform_device *pdev)
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cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_PHY, false);
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cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_CONTROLLER, false);
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#endif
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#ifdef CONFIG_ARCH_RK30
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*(unsigned int*)(USBGRF_UOC1_CON2+4) = ((1<<5)|((1<<5)<<16));
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#endif
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if (dwc_otg_device == 0)
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{
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dev_err(dev, "kmalloc of dwc_otg_device failed\n");
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@@ -1396,7 +1396,6 @@ void dwc_otg_hcd_free(struct usb_hcd *_hcd)
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return;
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}
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#ifdef DEBUG
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static void dump_urb_info(struct urb *_urb, char* _fn_name)
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{
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@@ -1511,17 +1510,6 @@ int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd,
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return retval;
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}
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#endif
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#if 1
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/*
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* Make sure the start of frame interrupt is enabled now that
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* we know we should have queued data. The SOF interrupt
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* handler automatically disables itself when idle to reduce
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* the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
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* for the disable
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*/
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dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0,
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DWC_SOF_INTR_MASK);
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#endif
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#ifdef DEBUG
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if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
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dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue");
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@@ -1544,6 +1532,17 @@ int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd,
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"Error status %d\n", retval);
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dwc_otg_hcd_qtd_free(qtd);
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}
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#if 1
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/*
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* Make sure the start of frame interrupt is enabled now that
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* we know we should have queued data. The SOF interrupt
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* handler automatically disables itself when idle to reduce
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* the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
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* for the disable
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*/
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dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0,
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DWC_SOF_INTR_MASK);
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#endif
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out:
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return retval;
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@@ -1912,7 +1912,7 @@ int dwc_otg_pcd_init(struct device *dev)
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pcd->vbus_status = 0;
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pcd->phy_suspend = 0;
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if(dwc_otg_is_device_mode(core_if))
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mod_timer(&pcd->check_vbus_timer, jiffies+(HZ<<2)); // delay 16 S +(HZ<<4)
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mod_timer(&pcd->check_vbus_timer, jiffies+(HZ<<4)); // delay 16 S
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DWC_PRINT("%s pass,everest\n", __func__);
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// dwc_otg_pcd_start_vbus_timer( pcd );
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return 0;
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