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hdmitx: optimise the clock divider

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PD#156734: optimise the clock divider of VID_PLL_DIV
This is a bridge of analog signal and digital signal module.
With VCO output 4.455Gbps/2160p60hzY420 12bits mode and the
ENCP needs 594MHz, there should divide half to reduce the
risk of HHI_VID_PLL_CLK_DIV.

Change-Id: If6965d64df1aa4b7cb4a8dd66847db3d5d17aea7
Signed-off-by: Zongdong Jiao <zongdong.jiao@amlogic.com>
This commit is contained in:
Zongdong Jiao
2018-03-02 18:24:07 +08:00
committed by Jianxin Pan
parent c85c24ded1
commit 63d9a28660
2 changed files with 6 additions and 1 deletions
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6
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
View File

@@ -624,6 +624,10 @@ static void set_hpll_od3_clk_div(int div_sel)
shift_val = 0x5294;
shift_sel = 2;
break;
case VID_PLL_DIV_3p25:
shift_val = 0x66cc;
shift_sel = 2;
break;
default:
pr_info("Error: clocks_set_vid_clk_div: Invalid parameter\n");
break;
@@ -813,7 +817,7 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_36[] = {
HDMI_3840x2160p60_16x9_Y420,
HDMI_3840x2160p50_16x9_Y420,
HDMI_VIC_END},
4455000, 1, 1, 1, VID_PLL_DIV_7p5, 1, 2, 1, -1},
4455000, 1, 1, 2, VID_PLL_DIV_3p25, 1, 2, 1, -1},
{{HDMI_3840x2160p24_16x9,
HDMI_3840x2160p25_16x9,
HDMI_3840x2160p30_16x9,

1
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.h
View File

@@ -37,6 +37,7 @@
#define VID_PLL_DIV_14 12
#define VID_PLL_DIV_15 13
#define VID_PLL_DIV_2p5 14
#define VID_PLL_DIV_3p25 15
#define GROUP_MAX 8
struct hw_enc_clk_val_group {