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rk2928: l2 data ram latency, write 1 cycle, read 3 cycles, setup 2 cycles

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黄涛
2012-08-08 11:25:30 +08:00
parent 7617d4a3e6
commit 64340b93df
1 changed files with 2 additions and 2 deletions
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4
arch/arm/mach-rk2928/common.c
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@@ -49,8 +49,8 @@ static void __init rk2928_l2_cache_init(void)
writel_relaxed(L2_LY_SET(1,L2_LY_SP_OFF)
|L2_LY_SET(1,L2_LY_RD_OFF)
|L2_LY_SET(1,L2_LY_WR_OFF), RK2928_L2C_BASE + L2X0_TAG_LATENCY_CTRL);
writel_relaxed(L2_LY_SET(4,L2_LY_SP_OFF)
|L2_LY_SET(6,L2_LY_RD_OFF)
writel_relaxed(L2_LY_SET(2,L2_LY_SP_OFF)
|L2_LY_SET(3,L2_LY_RD_OFF)
|L2_LY_SET(1,L2_LY_WR_OFF), RK2928_L2C_BASE + L2X0_DATA_LATENCY_CTRL);
/* L2X0 Prefetch Control */