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clk: rk3288: keep arm_gpll enable when rk3288 apll set_rate

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dkl
2014-05-13 14:21:45 +08:00
parent a40cc1f883
commit 64fddf4e59
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/rockchip/clk-pll.c
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@@ -1152,7 +1152,7 @@ static int clk_pll_set_rate_3288_apll(struct clk_hw *hw, unsigned long rate,
goto CHANGE_APLL;
}
#if 1
#if 0
if (clk_prepare(arm_gpll)) {
clk_err("fail to prepare arm_gpll path\n");
clk_unprepare(arm_gpll);
@@ -1246,8 +1246,8 @@ CHANGE_APLL:
if (sel_gpll) {
sel_gpll = 0;
clk_disable(arm_gpll);
clk_unprepare(arm_gpll);
//clk_disable(arm_gpll);
//clk_unprepare(arm_gpll);
}
//clk_debug("apll set loops_per_jiffy =%lu\n", loops_per_jiffy);