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Merge "ODROID-N2: vout: hdmitx: adjust hdmi timing and hpll over 2Gbps" into odroidn2-4.9.y-android

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This commit is contained in:
Joy Cho
2019-02-13 11:57:18 +09:00
committed by Gerrit Code Review
parent 4c752a48bb 35fb7dced2
commit 6503dc28bd
5 changed files with 30 additions and 7 deletions
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4
drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c
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@@ -1419,9 +1419,9 @@ static struct hdmi_format_para fmt_para_2560x1440p60_16x9 = {
.timing = {
.pixel_freq = 241500,
.frac_freq = 241500,
.h_freq = 98700,
.h_freq = 88790,
.v_freq = 60000,
.vsync_polarity = 0,
.vsync_polarity = 1,
.hsync_polarity = 1,
.h_active = 2560,
.h_total = 2720,

4
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
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@@ -700,8 +700,8 @@ static const struct reg_s tvregs_2560x1600p_60hz[] = {
{P_ENCP_VIDEO_MAX_LNCNT, 1645,},
{P_ENCP_VIDEO_HAVON_BEGIN, 80,},
{P_ENCP_VIDEO_HAVON_END, 2639,},
{P_ENCP_VIDEO_VAVON_BLINE, 38,},
{P_ENCP_VIDEO_VAVON_ELINE, 1637,},
{P_ENCP_VIDEO_VAVON_BLINE, 37,},
{P_ENCP_VIDEO_VAVON_ELINE, 1636,},
{P_ENCP_VIDEO_HSO_BEGIN, 0,},
{P_ENCP_VIDEO_HSO_END, 32,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},

10
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
View File

@@ -1508,7 +1508,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
FRONT_PORCH = 48;
HSYNC_PIXELS = 32;
BACK_PORCH = 80;
EOF_LINES = 2;
EOF_LINES = 3;
VSYNC_LINES = 6;
SOF_LINES = 38;
TOTAL_FRAMES = 4;
@@ -2120,6 +2120,14 @@ do { \
else
set_phy_by_mode(1);
break;
/* consider HPLL over 2Gbps */
case HDMI_2560x1600p60_8x5:
case HDMI_2560x1440p60_16x9:
if (hdev->para->cd == COLORDEPTH_24B)
set_phy_by_mode(2);
else
set_phy_by_mode(1);
break;
case HDMI_1080p60:
case HDMI_1080p50:
if (hdev->flag_3dfp)

4
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
View File

@@ -779,10 +779,10 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
5940000, 2, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
{{HDMI_2560x1600p60_8x5,
HDMI_VIC_END},
2685000, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
5405400, 2, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMI_2560x1440p60_16x9,
HDMI_VIC_END},
2415000, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
4830000, 2, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMI_2560x1080p60_64x27,
HDMI_VIC_END},
1855800, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},

15
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
View File

@@ -194,6 +194,21 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
break;
case 4830000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004c9);
if (frac_rate)
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
else
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00014000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
break;
case 4455000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b9);
if (frac_rate)