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clk: rk3288: set BW 20 when GPLL is 297m for HDMI

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dkl
2014-05-13 10:24:07 +08:00
parent 8f1f978a49
commit 654827f3f3
1 changed files with 10 additions and 0 deletions
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10
drivers/clk/rockchip/clk-pll.c
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@@ -1,5 +1,6 @@
#include <linux/slab.h>
#include <asm/io.h>
#include <linux/rockchip/cpu.h>
#include "clk-ops.h"
#include "clk-pll.h"
@@ -679,6 +680,15 @@ static int clk_pll_set_rate_3188plus(struct clk_hw *hw, unsigned long rate,
clk_set++;
}
if (cpu_is_rk3288() && (rate == 297*MHZ)) {
if((strncmp(__clk_get_name(hw->clk), "clk_gpll",
strlen("clk_gpll")) == 0)) {
printk("rk3288 set GPLL BW 20 for HDMI!\n");
clk_set->pllcon2 = RK3188_PLL_CLK_BWADJ_SET(20);
}
}
if (clk_set->rate == rate) {
ret = _pll_clk_set_rate_3188plus(clk_set, hw);
clk_debug("pll %s set rate=%lu OK!\n", __clk_get_name(hw->clk),