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clk: rockchip: rk3399: add SCLK_PCIEPHY_REF100M for PCIe

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Change-Id: Iead548d47a627745267acbcc73d401f73c68a702
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This commit is contained in:
Xing Zheng
2016-04-07 11:29:59 +08:00
committed by Gerrit Code Review
parent da771ed410
commit 65fac424f2
2 changed files with 2 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3399.c
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@@ -878,7 +878,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(6), 2, GFLAGS),
COMPOSITE_NOMUX(0, "clk_pciephy_ref100m", "npll", 0,
COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0,
RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
RK3399_CLKGATE_CON(12), 6, GFLAGS),
MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,

1
include/dt-bindings/clock/rk3399-cru.h
View File

@@ -130,6 +130,7 @@
#define SCLK_DPHY_TX1RX1_CFG 164
#define SCLK_DPHY_RX0_CFG 165
#define SCLK_RMII_SRC 166
#define SCLK_PCIEPHY_REF100M 167
#define DCLK_VOP0 180
#define DCLK_VOP1 181