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Merge commit '65ecb0038c20de2af41860ae29b14d741710e07e'

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* commit '65ecb0038c20de2af41860ae29b14d741710e07e':
  arm64: dts: rockchip: rk817/rk809: Changing the implementation of pin functions
  mfd: rk809/rk817: Modify the switching method of the PMIC sleep function
  drivers: rkflash: Check unaligned sfc_request
  media: rockchip: isp: fix b3dldc for isp35
  media: rockchip: aiisp: add ioctl to clear unused iq params
  media: rockchip: isp: support aibnr l2 for isp35
  media: rockchip: aiisp: optimize aibnr out memory
  media: rockchip: isp: optimize memory for isp35 aiisp
  media: rockchip: isp: aiisp switch for isp35 multi sensor

Change-Id: I7eb9b59560578f00ee1b278bd6049ca613e21a97
This commit is contained in:
Tao Huang
2025-08-04 09:30:36 +08:00
parent 79e3d457f9 65ecb0038c
commit 672c56f23a
55 changed files with 724 additions and 258 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm64/boot/dts/rockchip/px30-ad-d6-anx6345.dts
View File

@@ -184,9 +184,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-robot-linux.dts
View File

@@ -150,9 +150,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-robot-no-gpu-linux.dts
View File

@@ -150,9 +150,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dtsi
View File

@@ -254,9 +254,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/px30-z7-a0-rk618-dsi.dts
View File

@@ -281,9 +281,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

4
arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi
View File

@@ -281,8 +281,8 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_null>;
rockchip,system-power-controller;
wakeup-source;

6
arch/arm64/boot/dts/rockchip/rk3326-863-lp3-v10.dtsi
View File

@@ -302,9 +302,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3326-86v-v10.dts
View File

@@ -252,9 +252,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v10.dts
View File

@@ -389,9 +389,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v11-i2s-dmic.dts
View File

@@ -399,9 +399,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v11.dts
View File

@@ -389,9 +389,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v12.dts
View File

@@ -389,9 +389,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10-robot-linux.dts
View File

@@ -158,9 +158,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10-robot-no-gpu-linux.dts
View File

@@ -153,9 +153,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10.dtsi
View File

@@ -350,9 +350,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3358-evb-ddr3.dtsi
View File

@@ -535,9 +535,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3358m-automotive-ddr3-v11.dtsi
View File

@@ -231,9 +231,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3358m-vehicle-ddr3.dtsi
View File

@@ -616,9 +616,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3368a-817-tablet-bnd.dts
View File

@@ -364,9 +364,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_slp>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3368a-817-tablet.dts
View File

@@ -562,9 +562,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_slp>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts
View File

@@ -628,9 +628,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_gpio>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi
View File

@@ -19,9 +19,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_gpio>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts
View File

@@ -548,9 +548,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_gpio>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi
View File

@@ -19,9 +19,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_gpio>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3562j-core-ddr4-v10.dts
View File

@@ -123,9 +123,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_gpio>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts
View File

@@ -395,9 +395,9 @@
// pinctrl-names = "default", "pmic-sleep",
// "pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
// pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
// pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
// pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
// pinctrl-1 = <&soc_slppin_slp>;
// pinctrl-2 = <&soc_slppin_gpio>;
// pinctrl-3 = <&soc_slppin_gpio>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w6.dts
View File

@@ -294,9 +294,9 @@
// pinctrl-names = "default", "pmic-sleep",
// "pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
// pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
// pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
// pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
// pinctrl-1 = <&soc_slppin_slp>;
// pinctrl-2 = <&soc_slppin_gpio>;
// pinctrl-3 = <&soc_slppin_gpio>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3566-rk817-eink.dts
View File

@@ -255,9 +255,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_gpio>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts
View File

@@ -584,9 +584,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_gpio>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts
View File

@@ -402,9 +402,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_gpio>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-v10.dts
View File

@@ -508,9 +508,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_gpio>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts
View File

@@ -513,9 +513,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_gpio>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

6
arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi
View File

@@ -1114,9 +1114,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>;
pinctrl-3 = <&soc_slppin_gpio>;
rockchip,system-power-controller;
wakeup-source;

6
arch/arm64/boot/dts/rockchip/rk3568-toybrick.dtsi
View File

@@ -1145,9 +1145,9 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_pin>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_pin>, <&rk817_slppin_rst>;
pinctrl-1 = <&soc_slppin_slp>;
pinctrl-2 = <&soc_slppin_pin>;
pinctrl-3 = <&soc_slppin_pin>;
rockchip,system-power-controller;
wakeup-source;

4
arch/arm64/boot/dts/rockchip/rv1126bp-evb-v14.dtsi
View File

@@ -162,8 +162,8 @@
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_gpio>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-1 = <&soc_slppin_gpio>;
pinctrl-2 = <&soc_slppin_gpio>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;

30
drivers/media/platform/rockchip/aiisp/aiisp.c
View File

@@ -1474,9 +1474,7 @@ static void rkaiisp_run_cfg(struct rkaiisp_device *aidev, u32 run_idx)
rkaiisp_gen_slice_param(aidev, model_cfg, sig_width);
rkaiisp_determine_size(aidev, model_cfg);
iir_stride = CEIL_BY(ispbuf->iir_width, 16);
iir_stride = CEIL_BY(iir_stride * 9 / 4, 16);
iir_stride = iir_stride >> 1;
iir_stride = ispbuf->bnr_buf.u.v35.aiisp.buf_stride >> 1;
rkaiisp_write(aidev, AIISP_MI_CHN0_WR_STRIDE, iir_stride / 2, false);
}
} else {
@@ -1513,9 +1511,7 @@ static void rkaiisp_run_cfg(struct rkaiisp_device *aidev, u32 run_idx)
rkaiisp_gen_slice_param(aidev, model_cfg, ispbuf->sig_width[0]);
rkaiisp_determine_size(aidev, model_cfg);
iir_stride = CEIL_BY(ispbuf->iir_width, 16);
iir_stride = CEIL_BY(iir_stride * 9 / 4, 16);
iir_stride = iir_stride >> 1;
iir_stride = ispbuf->bnr_buf.u.v35.aiisp.buf_stride >> 1;
rkaiisp_write(aidev, AIISP_MI_CHN0_WR_STRIDE, iir_stride / 2, false);
}
}
@@ -1627,7 +1623,7 @@ static void rkaiisp_run_start(struct rkaiisp_device *aidev)
rkaiisp_update_list_reg(aidev);
}
static void rkaiisp_get_new_iqparam(struct rkaiisp_device *aidev)
static int rkaiisp_get_new_iqparam(struct rkaiisp_device *aidev)
{
struct rkaiisp_params *iq_params, *old_params;
struct rkaiisp_buffer *cur_buf = NULL;
@@ -1641,7 +1637,7 @@ static void rkaiisp_get_new_iqparam(struct rkaiisp_device *aidev)
struct rkaiisp_buffer, queue);
if (!cur_buf) {
spin_unlock_irqrestore(&aidev->config_lock, flags);
return;
return -1;
}
list_del(&cur_buf->queue);
@@ -1676,8 +1672,22 @@ static void rkaiisp_get_new_iqparam(struct rkaiisp_device *aidev)
aidev->model_runcnt = iq_params->model_runcnt;
rkaiisp_cfg_other_iqparam(aidev, &iq_params->other_cfg);
}
return 0;
}
static int rkaiisp_clear_iqparams(struct rkaiisp_device *aidev)
{
int i;
for (i = 0; i < aidev->iq_parambuf_num; i++) {
if (rkaiisp_get_new_iqparam(aidev) != 0)
break;
}
v4l2_dbg(1, rkaiisp_debug, &aidev->v4l2_dev,
"clear unused iq params\n");
return 0;
}
void rkaiisp_trigger(struct rkaiisp_device *aidev)
{
@@ -1951,6 +1961,9 @@ static long rkaiisp_ioctl_default(struct file *file, void *fh,
ret = 0;
}
break;
case RKAIISP_CMD_CLEAR_IQPARAMS:
ret = rkaiisp_clear_iqparams(aidev);
break;
default:
ret = -EINVAL;
}
@@ -1992,6 +2005,7 @@ static int rkaiisp_vb2_queue_setup(struct vb2_queue *vq,
sizes[0] = sizeof(struct rkaiisp_params) + aidev->para_size * aidev->max_runcnt;
aidev->vdev_fmt.fmt.meta.buffersize = sizes[0];
aidev->iq_parambuf_num = *num_buffers;
INIT_LIST_HEAD(&aidev->params);

2
drivers/media/platform/rockchip/aiisp/aiisp.h
View File

@@ -170,6 +170,8 @@ struct rkaiisp_device {
bool showreg;
bool init_buf;
bool is_state_err;
u8 iq_parambuf_num;
};
extern int rkaiisp_debug;

3
drivers/media/platform/rockchip/isp/common.c
View File

@@ -210,6 +210,8 @@ void rkisp_update_regs(struct rkisp_device *dev, u32 start, u32 end)
i == ISP32_BP_RESIZE_CTRL ||
i == ISP3X_SELF_RESIZE_CTRL) && *val == 0)
*val = CIF_RSZ_CTRL_CFG_UPD;
if (i == ISP3X_ISP_IMSC)
writel(*val, base + ISP3X_ISP_ICR);
writel(*val, base + i);
if (hw->unite == ISP_UNITE_TWO) {
val = dev->sw_base_addr + i + RKISP_ISP_SW_MAX_SIZE;
@@ -338,6 +340,7 @@ void rkisp_free_buffer(struct rkisp_device *dev,
dma_buf_put(buf->dbuf);
g_ops->put(buf->mem_priv);
buf->size = 0;
buf->stride = 0;
buf->index = -1;
buf->dbuf = NULL;
buf->vaddr = NULL;

1
drivers/media/platform/rockchip/isp/common.h
View File

@@ -137,6 +137,7 @@ struct rkisp_dummy_buffer {
void *mem_priv;
void *vaddr;
u32 size;
u32 stride;
int dma_fd;
int index;
bool is_need_vaddr;

7
drivers/media/platform/rockchip/isp/dev.h
View File

@@ -315,6 +315,12 @@ struct rkisp_device {
bool is_aiisp_stop;
bool is_aiisp_sync;
bool is_aiisp_yuv;
bool is_aiisp_first_frame;
bool is_aiisp_l2;
bool is_aiisp_l2_st;
bool is_aiisp_l2_first_cfg;
bool is_aiisp_l2_init;
bool is_aiisp_l2_waiting;
bool is_frm_rd;
bool is_multi_one_sync;
bool is_wait_aiq;
@@ -325,6 +331,7 @@ struct rkisp_device {
u32 hdr_wrap_line;
u32 aiisp_stop_seq;
u32 aiisp_fe_seq;
u8 multi_mode;
u8 multi_index;

2
drivers/media/platform/rockchip/isp/isp_ispp.h
View File

@@ -72,9 +72,7 @@ enum rkisp_ispp_reg_stat {
struct frame_debug_info {
u64 timestamp;
u64 timestamp_be;
u32 interval;
u32 interval_be;
u32 delay;
u32 id;
u32 frameloss;

5
drivers/media/platform/rockchip/isp/isp_params.c
View File

@@ -313,6 +313,11 @@ static void rkisp_params_vb2_stop_streaming(struct vb2_queue *vq)
}
dev->is_aiisp_yuv = false;
dev->is_aiisp_en = false;
dev->is_aiisp_first_frame = false;
dev->is_aiisp_l2 = false;
dev->is_aiisp_l2_st = false;
dev->is_aiisp_l2_first_cfg = false;
dev->is_aiisp_l2_init = false;
dev->is_aiisp_stop = false;
dev->is_aiisp_stopping = false;
memset(&dev->aiisp_cfg, 0, sizeof(dev->aiisp_cfg));

2
drivers/media/platform/rockchip/isp/isp_params.h
View File

@@ -60,6 +60,8 @@ struct rkisp_isp_params_ops {
int (*get_aiawb_buffd)(struct rkisp_isp_params_vdev *params_vdev, void *arg);
void (*vpsl_update_regs)(struct rkisp_isp_params_vdev *params_vdev);
void (*aiisp_switch)(struct rkisp_isp_params_vdev *params_vdev, bool on);
void (*aiisp_l2_enter)(struct rkisp_isp_params_vdev *params_vdev, struct rkisp_aiisp_st *st);
void (*aiisp_l2_exit)(struct rkisp_isp_params_vdev *params_vdev);
};
/*

337
drivers/media/platform/rockchip/isp/isp_params_v35.c
View File

@@ -4002,6 +4002,9 @@ isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev,
arg->btnr_ldc_wrap_ext_bound_offset;
isp3_param_write(params_vdev, value, ISP35_B3DLDC_EXTBOUND1, id);
value = arg->b3dldc_last;
isp3_param_write(params_vdev, value, ISP35_B3DLDC_FFFF_OFF, id);
ctrl = 0;
if (arg->b3dldch_en) {
value = priv->buf_b3dldc[id][buf_idx].dma_addr + head->data_oft;
@@ -4029,6 +4032,8 @@ isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev,
ISP35_B3DLDC_EN;
}
isp3_param_write(params_vdev, ctrl, ISP35_B3DLDC_CTRL, id);
if (dev->hw_dev->is_single)
isp3_param_set_bits(params_vdev, MI_WR_CTRL2, ISP3X_BAY3D_RDSELF_UPD, id);
}
static void
@@ -4050,6 +4055,10 @@ isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
dev_err(dev->dev, "no bay3d buffer available\n");
return;
}
value = priv->bay3d_iir_stride;
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_LENGTH, id);
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_RD_LENGTH, id);
isp3_param_write(params_vdev, value, ISP35_B3DLDC_WR_STRIDE, id);
priv->bay3d_iir_idx = 0;
priv->bay3d_iir_cur_idx = 0;
@@ -4058,24 +4067,23 @@ isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
value = priv->buf_bay3d_iir[0].dma_addr + value * id;
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_RD_BASE, id);
if (priv->bay3d_iir_rw_fmt == 3) {
isp3_param_write(params_vdev, priv->bay3d_iir_pk_stride, ISP3X_MI_BAY3D_IIR_WR_LENGTH, id);
isp3_param_write(params_vdev, value, ISP35_B3DLDC_WR_ADDR, id);
if (b3dldc_ctrl & ISP35_B3DLDC_EN) {
b3dldc_ctrl |= ISP35_B3DLDC_FORCE_UPD;
isp3_param_write(params_vdev, b3dldc_ctrl, ISP35_B3DLDC_CTRL, id);
}
value += priv->bay3d_iir_offs;
value += priv->bay3d_iir_pk_offs;
}
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_BASE, id);
if (priv->buf_aiisp[0].mem_priv) {
priv->aiisp_cur_idx = 0;
value = priv->buf_aiisp[0].dma_addr + value * id;
isp3_param_write(params_vdev, value, ISP39_AIISP_RD_BASE, id);
value = priv->buf_aiisp[0].stride;
isp3_param_write(params_vdev, value, ISP3X_MI_DBR_RD_LENGTH, id);
}
value = priv->bay3d_iir_stride;
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_LENGTH, id);
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_RD_LENGTH, id);
isp3_param_write(params_vdev, value, ISP3X_MI_DBR_RD_LENGTH, id);
isp3_param_write(params_vdev, value, ISP35_B3DLDC_WR_STRIDE, id);
priv->bay3d_ds_idx = 0;
priv->bay3d_ds_cur_idx = 0;
@@ -4594,6 +4602,9 @@ void __isp_isr_other_config(struct rkisp_isp_params_vdev *params_vdev,
if (type == RKISP_PARAMS_IMD && dev->is_aiisp_en)
return;
if (module_cfg_update & ISP35_MODULE_BAY3D_L2 && dev->is_aiisp_l2_st)
isp_bay3d_config(params_vdev, &new_params->others.bay3d_l2_cfg, id);
if (module_cfg_update & ISP35_MODULE_CAC)
isp_cac_config(params_vdev, &new_params->others.cac_cfg, id);
if (module_cfg_update & ISP35_MODULE_LSC)
@@ -5309,7 +5320,7 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
struct rkisp_dummy_buffer *buf;
u32 w = isp_sdev->out_crop.width;
u32 h = isp_sdev->out_crop.height;
u32 iir_rw_fmt, size, val, w16, w32, w128, iir_size = 0;
u32 iir_rw_fmt, size, stride, w16, w32, w128, iir_size = 0;
int ret, i, cnt;
INIT_LIST_HEAD(&priv->iir_list);
@@ -5327,32 +5338,37 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
w32 = ALIGN(w, 32);
w128 = ALIGN(w, 128);
priv->bay3d_iir_stride = 0;
priv->bay3d_iir_offs = 0;
priv->bay3d_iir_pk_stride = 0;
priv->bay3d_iir_pk_offs = 0;
switch (iir_rw_fmt) {
case 0:
val = w16 * 7 / 4;
size = val * h;
stride = ALIGN(w16 * 7 / 4, 16);
break;
case 1:
size = w16 * h * 2;
stride = ALIGN(w16 * 2, 16);
break;
case 2:
case 4:
val = ALIGN(w16 * 9 / 4, 16);
size = val * h;
priv->bay3d_iir_stride = val;
stride = ALIGN(w16 * 9 / 4, 16);
priv->bay3d_iir_stride = stride;
break;
case 3:
val = ALIGN((w32 + w128 / 8) * 2, 16);
size = val * h;
priv->bay3d_iir_stride = val;
priv->bay3d_iir_offs = w32 * 2;
/* pk_wr */
stride = ALIGN(w128 / 8 * 2, 16);
priv->bay3d_iir_pk_stride = stride;
/* iir_rw + pk_rd */
stride = ALIGN((w32 + w128 / 8) * 2, 16);
priv->bay3d_iir_stride = stride;
/* iir_rw + pk_rd + pk_wr */
priv->bay3d_iir_pk_offs = priv->bay3d_iir_stride * h;
size = (priv->bay3d_iir_stride + priv->bay3d_iir_pk_stride) * h;
break;
default:
dev_err(dev->dev, "bay3d iir_rw_fmt:%d error\n", iir_rw_fmt);
return -EINVAL;
}
size = ALIGN(size, 16);
if (iir_rw_fmt != 3)
size = ALIGN(stride * h, 16);
priv->bay3d_iir_size = size;
if (dev->unite_div > ISP_UNITE_DIV1)
size *= dev->unite_div;
@@ -5364,6 +5380,7 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
for (i = 0; i < cnt; i++) {
buf = &priv->buf_bay3d_iir[i];
buf->size = size;
buf->stride = stride;
buf->is_need_dbuf = true;
buf->is_need_dmafd = true;
ret = rkisp_alloc_buffer(dev, buf);
@@ -5381,10 +5398,11 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
priv->bay3d_iir_cnt = cnt;
bnrbuf->iir.buf_cnt = cnt;
bnrbuf->iir.buf_size = size;
bnrbuf->iir.buf_stride = stride;
iir_size = size;
val = (w16 * 36 / 8 + 31) / 32 * 4;
size = ALIGN(val * ((h + 7) / 8), 16);
stride = (w16 * 36 / 8 + 31) / 32 * 4;
size = ALIGN(stride * ((h + 7) / 8), 16);
priv->bay3d_ds_size = size;
if (dev->unite_div > ISP_UNITE_DIV1)
size *= dev->unite_div;
@@ -5394,6 +5412,7 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
for (i = 0; i < cnt; i++) {
buf = &priv->buf_bay3d_ds[i];
buf->size = size;
buf->stride = stride;
buf->is_need_dbuf = true;
buf->is_need_dmafd = true;
ret = rkisp_alloc_buffer(dev, buf);
@@ -5407,9 +5426,10 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
priv->bay3d_ds_cnt = cnt;
bnrbuf->u.v35.ds.buf_cnt = cnt;
bnrbuf->u.v35.ds.buf_size = size;
bnrbuf->u.v35.ds.buf_stride = stride;
val = (((w + 31) / 32 + 1) / 2 * 2 + 3) / 4 * 4;
size = ALIGN(val * ((h + 31) / 32), 16);
stride = (((w + 31) / 32 + 1) / 2 * 2 + 3) / 4 * 4;
size = ALIGN(stride * ((h + 31) / 32), 16);
priv->bay3d_wgt_size = size;
if (dev->unite_div > ISP_UNITE_DIV1)
size *= dev->unite_div;
@@ -5418,6 +5438,7 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
for (i = 0; i < cnt; i++) {
buf = &priv->buf_bay3d_wgt[i];
buf->size = size;
buf->stride = stride;
buf->is_need_dbuf = true;
buf->is_need_dmafd = true;
ret = rkisp_alloc_buffer(dev, buf);
@@ -5431,13 +5452,17 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
priv->bay3d_wgt_cnt = cnt;
bnrbuf->u.v35.wgt.buf_cnt = cnt;
bnrbuf->u.v35.wgt.buf_size = size;
bnrbuf->u.v35.wgt.buf_stride = stride;
stride = w32 * 2;
size = stride * h;
cnt = bnrbuf->u.v35.aiisp.buf_cnt;
if (cnt >= RKISP_BUFFER_MAX)
cnt = RKISP_BUFFER_MAX - 1;
for (i = 0; i < cnt && iir_size; i++) {
buf = &priv->buf_aiisp[i];
buf->size = iir_size;
buf->size = size;
buf->stride = stride;
buf->is_need_dbuf = true;
buf->is_need_dmafd = true;
ret = rkisp_alloc_buffer(dev, buf);
@@ -5450,9 +5475,14 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
}
priv->aiisp_cnt = cnt;
bnrbuf->u.v35.aiisp.buf_cnt = cnt;
bnrbuf->u.v35.aiisp.buf_size = iir_size;
bnrbuf->u.v35.aiisp.buf_size = size;
bnrbuf->u.v35.aiisp.buf_stride = stride;
size = ALIGN(w * h / 4, 16);
if (bnrbuf->u.v35.gain_mode)
stride = w / 8;
else
stride = w / 4;
size = ALIGN(stride * h, 16);
priv->gain_size = size;
if (dev->unite_div > ISP_UNITE_DIV1)
size *= dev->unite_div;
@@ -5462,6 +5492,7 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
for (i = 0; i < cnt; i++) {
buf = &priv->buf_gain[i];
buf->size = size;
buf->stride = stride;
buf->is_need_dbuf = true;
buf->is_need_dmafd = true;
ret = rkisp_alloc_buffer(dev, buf);
@@ -5479,10 +5510,11 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
priv->gain_cnt = cnt;
bnrbuf->u.v35.gain.buf_cnt = cnt;
bnrbuf->u.v35.gain.buf_size = size;
bnrbuf->u.v35.gain.buf_stride = stride;
val = ALIGN(w / 4, 16);
priv->aipre_gain_stride = val;
size = ALIGN(val * (h / 2), 16);
stride = ALIGN(w / 4, 16);
priv->aipre_gain_stride = stride;
size = ALIGN(stride * (h / 2), 16);
if (dev->unite_div > ISP_UNITE_DIV1)
size *= dev->unite_div;
cnt = bnrbuf->u.v35.aipre_gain.buf_cnt;
@@ -5491,6 +5523,7 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
for (i = 0; i < cnt; i++) {
buf = &priv->buf_aipre_gain[i];
buf->size = size;
buf->stride = stride;
buf->is_need_dbuf = true;
buf->is_need_dmafd = true;
ret = rkisp_alloc_buffer(dev, buf);
@@ -5508,6 +5541,7 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
priv->aipre_gain_cnt = cnt;
bnrbuf->u.v35.aipre_gain.buf_cnt = cnt;
bnrbuf->u.v35.aipre_gain.buf_size = size;
bnrbuf->u.v35.aipre_gain.buf_stride = stride;
priv->bay3d_iir_rw_fmt = iir_rw_fmt;
priv->yraw_sel = !!bnrbuf->u.v35.yraw_sel;
@@ -5515,7 +5549,8 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
if (ret)
goto err_vpsl;
size = ALIGN(w, 16) * h;
stride = ALIGN(w, 16);
size = stride * h;
if (dev->unite_div > ISP_UNITE_DIV1)
size *= dev->unite_div;
cnt = bnrbuf->u.v35.y_src.buf_cnt;
@@ -5524,6 +5559,7 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
for (i = 0; i < cnt; i++) {
buf = &priv->buf_y_src[i];
buf->size = size;
buf->stride = stride;
buf->is_need_dbuf = true;
buf->is_need_dmafd = true;
ret = rkisp_alloc_buffer(dev, buf);
@@ -5543,7 +5579,40 @@ rkisp_params_init_bnr_buf_v35(struct rkisp_isp_params_vdev *params_vdev,
priv->y_src_cnt = cnt;
bnrbuf->u.v35.y_src.buf_cnt = cnt;
bnrbuf->u.v35.y_src.buf_size = size;
bnrbuf->u.v35.y_src.buf_stride = stride;
if (bnrbuf->u.v35.aibnr_l2) {
buf = &priv->buf_bay3d_iir_l2;
buf->size = bnrbuf->iir.buf_size;
ret = rkisp_alloc_buffer(dev, buf);
if (ret) {
dev_err(dev->dev, "alloc bay3d iir l2 buf fail:%d\n", ret);
goto err_iir_l2;
}
buf = &priv->buf_bay3d_ds_l2;
buf->size = bnrbuf->u.v35.ds.buf_size;
ret = rkisp_alloc_buffer(dev, buf);
if (ret) {
dev_err(dev->dev, "alloc bay3d ds l2 buf fail:%d\n", ret);
goto err_ds_l2;
}
buf = &priv->buf_bay3d_wgt_l2;
buf->size = bnrbuf->u.v35.wgt.buf_size;
ret = rkisp_alloc_buffer(dev, buf);
if (ret) {
dev_err(dev->dev, "alloc bay3d wgt l2 buf fail:%d\n", ret);
goto err_wgt_l2;
}
priv->is_aiisp_l2_buf = true;
}
return 0;
err_wgt_l2:
rkisp_free_buffer(dev, &priv->buf_bay3d_ds_l2);
err_ds_l2:
rkisp_free_buffer(dev, &priv->buf_bay3d_iir_l2);
err_iir_l2:
i = priv->y_src_cnt;
err_y_src:
for (i -= 1; i >= 0; i--) {
buf = &priv->buf_y_src[i];
@@ -5693,6 +5762,11 @@ rkisp_params_stream_stop_v35(struct rkisp_isp_params_vdev *params_vdev)
struct rkisp_device *dev = params_vdev->dev;
int i;
rkisp_free_buffer(dev, &priv->buf_bay3d_wgt_l2);
rkisp_free_buffer(dev, &priv->buf_bay3d_ds_l2);
rkisp_free_buffer(dev, &priv->buf_bay3d_iir_l2);
priv->is_aiisp_l2_buf = false;
for (i = 0; i < priv->y_src_cnt; i++)
rkisp_free_buffer(dev, &priv->buf_y_src[i]);
priv->y_src_cnt = 0;
@@ -6129,6 +6203,8 @@ rkisp_params_aiisp_event_v35(struct rkisp_isp_params_vdev *params_vdev, u32 irq)
}
is_event_queue = false;
}
if (dev->is_aiisp_first_frame && is_event_queue)
dev->is_aiisp_first_frame = false;
buf = priv->pbuf_vpsl;
if (buf)
@@ -6191,9 +6267,13 @@ rkisp_params_aiisp_start_v35(struct rkisp_isp_params_vdev *params_vdev,
if (st->aiisp_index >= 0) {
priv->pbuf_aiisp = &priv->buf_aiisp[st->aiisp_index];
aiisp_rd = priv->pbuf_aiisp->dma_addr;
val = priv->pbuf_aiisp->stride;
rkisp_write(dev, ISP3X_MI_DBR_RD_LENGTH, val, false);
} else {
/* NPU no output, just using iir data */
aiisp_rd = buf->dma_addr;
val = priv->bay3d_iir_stride;
rkisp_write(dev, ISP3X_MI_DBR_RD_LENGTH, val, false);
}
priv->aiisp_cur_idx = st->aiisp_index;
@@ -6235,13 +6315,13 @@ rkisp_params_aiisp_start_v35(struct rkisp_isp_params_vdev *params_vdev,
val = priv->pbuf_gain_rd->dma_addr;
if (!params_vdev->is_hdr) {
rkisp_write(dev, ISP3X_MI_RAW0_RD_BASE, val, false);
if (dev->hw_dev->is_single) {
if (dev->hw_dev->is_single && !dev->is_aiisp_stop) {
rkisp_set_bits(dev, ISP3X_CSI2RX_RAW_RD_CTRL, 0, ISP35_RX0_FORCE_UPD, true);
rkisp_set_bits(dev, ISP3X_MI_WR_CTRL2, 0, ISP3X_DBR_RDSELF_UPD, true);
}
} else {
rkisp_write(dev, ISP35_B3DLDCH_RD_BASE, val, false);
if (dev->hw_dev->is_single) {
if (dev->hw_dev->is_single && !dev->is_aiisp_stop) {
val = ISP3X_DBR_RDSELF_UPD | ISP3X_BAY3D_RDSELF_UPD;
rkisp_set_bits(dev, ISP3X_MI_WR_CTRL2, 0, val, true);
}
@@ -6328,12 +6408,16 @@ rkisp_params_aiisp_switch_v35(struct rkisp_isp_params_vdev *params_vdev, bool on
val &= ~ISP35_AIPRE_ITS_FORCE_UPD;
rkisp_write(dev, ISP35_AI_CTRL, val, false);
val = rkisp_read(dev, ISP3X_MI_BAY3D_IIR_RD_BASE_SHD, true);
rkisp_write(dev, ISP3X_MI_BAY3D_IIR_WR_BASE, val, false);
if (dev->hw_dev->is_single) {
val = rkisp_read(dev, ISP3X_MI_BAY3D_IIR_RD_BASE_SHD, true);
rkisp_write(dev, ISP3X_MI_BAY3D_IIR_WR_BASE, val, false);
val = ISP3X_BAY3D_IIRSELF_UPD | ISP3X_BAY3D_RDSELF_UPD |
ISP3X_GAINSELF_UPD;
rkisp_set_bits(dev, MI_WR_CTRL2, 0, val, false);
} else {
val = rkisp_read_reg_cache(dev, ISP3X_MI_BAY3D_IIR_RD_BASE);
rkisp_write(dev, ISP3X_MI_BAY3D_IIR_WR_BASE, val, false);
}
rkisp_stats_first_ddr_config(stats_vdev);
@@ -6385,10 +6469,9 @@ rkisp_params_aiisp_switch_v35(struct rkisp_isp_params_vdev *params_vdev, bool on
rkisp_write(dev, ISP35_AI_CTRL, val, false);
params_vdev->cur_fe_frame_id = params_vdev->cur_frame_id;
if (IS_HDR_RDBK(dev->rd_mode)) {
dev->is_first_frame = true;
if (IS_HDR_RDBK(dev->rd_mode))
dev->irq_ends_mask = ISP_FRAME_BNR | ISP_FRAME_VPSL;
}
dev->is_aiisp_first_frame = true;
}
}
@@ -6422,7 +6505,7 @@ rkisp_params_isr_v35(struct rkisp_isp_params_vdev *params_vdev, u32 isp_mis)
val += i * priv->bay3d_iir_size;
if (priv->bay3d_iir_rw_fmt == 3) {
isp3_param_write(params_vdev, val, ISP35_B3DLDC_WR_ADDR, i);
val += priv->bay3d_iir_offs;
val += priv->bay3d_iir_pk_offs;
}
isp3_param_write(params_vdev, val, ISP3X_MI_BAY3D_IIR_WR_BASE, i);
}
@@ -6488,10 +6571,14 @@ rkisp_params_isr_v35(struct rkisp_isp_params_vdev *params_vdev, u32 isp_mis)
rkisp_params_clear_fstflg(params_vdev);
rkisp_dmarx_get_frame(dev, &i, NULL, NULL, true);
if (isp_mis & ISP3X_BAY3D_FRM_END && dev->is_aiisp_en) {
if (isp_mis & ISP3X_BAY3D_FRM_END && dev->is_aiisp_en && !dev->is_aiisp_l2_st) {
dev->aiisp_fe_seq = i;
rkisp_params_aiisp_update_buf(params_vdev);
if (!IS_HDR_RDBK(dev->rd_mode))
if (!IS_HDR_RDBK(dev->rd_mode)) {
if (dev->is_aiisp_l2 && !dev->is_aiisp_l2_init)
return;
rkisp_params_cfg_v35(params_vdev, i + 1, RKISP_PARAMS_IMD);
}
} else if (isp_mis & CIF_ISP_FRAME && !IS_HDR_RDBK(dev->rd_mode) &&
!params_vdev->rdbk_times && !dev->is_aiisp_en) {
rkisp_params_cfg_v35(params_vdev, i + 1, RKISP_PARAMS_ALL);
@@ -6504,6 +6591,7 @@ void rkisp_params_vpsl_mi_isr_v35(struct rkisp_isp_params_vdev *params_vdev, u32
struct rkisp_isp_params_val_v35 *priv = params_vdev->priv_val;
struct rkisp_device *dev = params_vdev->dev;
unsigned long lock_flags = 0;
bool is_event = false;
if (!dev->is_aiisp_en)
return;
@@ -6517,10 +6605,170 @@ void rkisp_params_vpsl_mi_isr_v35(struct rkisp_isp_params_vdev *params_vdev, u32
vpsl_update_buf(params_vdev, priv->pbuf_vpsl, true);
priv->vpsl_cur_idx = priv->vpsl_idx;
}
if (dev->is_aiisp_sync)
rkisp_check_idle(dev, ISP_FRAME_VPSL);
is_event = true;
}
spin_unlock_irqrestore(&priv->buf_lock, lock_flags);
if (is_event)
rkisp_check_idle(dev, ISP_FRAME_VPSL);
}
static void
rkisp_params_aiisp_l2_enter_v35(struct rkisp_isp_params_vdev *params_vdev,
struct rkisp_aiisp_st *st)
{
struct rkisp_isp_params_val_v35 *priv = params_vdev->priv_val;
struct rkisp_device *dev = params_vdev->dev;
struct rkisp_hw_dev *hw = dev->hw_dev;
u32 val;
if (dev->is_aiisp_l2_first_cfg) {
if (!priv->is_aiisp_l2_buf) {
dev_err(dev->dev, "no alloc bay3d l2 buf\n");
return;
}
dev->is_aiisp_l2_first_cfg = false;
rkisp_set_bits(dev, ISP3X_ISP_CTRL1, 0, ISP3X_RAW3D_FST_FRAME, false);
}
dev->is_aiisp_l2_st = true;
rkisp_clear_bits(dev, ISP33_BAY3D_CTRL0, 0xffff0002, false);
rkisp_params_aiisp_start_v35(params_vdev, st);
/* aiisp output 16bit, config dmarx uncompact 16bit */
val = rkisp_read(dev, CSI2RX_DATA_IDS_1, false);
val &= ~SW_CSI_ID0(0xff);
val |= CIF_CSI2_DT_RAW16;
rkisp_write(dev, CSI2RX_DATA_IDS_1, val, false);
val = dev->isp_sdev.out_crop.height << 16 | dev->isp_sdev.out_crop.width;
rkisp_write(dev, CSI2RX_RAW_RD_PIC_SIZE, val, false);
val = rkisp_read_reg_cache(dev, ISP3X_MI_DBR_RD_LENGTH);
rkisp_write(dev, ISP3X_MI_RAWS_RD_LENGTH, val, false);
/* disable aipre and vpsl output */
val = rkisp_read(dev, ISP35_AI_CTRL, false);
val &= ~(ISP35_AIISP_ST | ISP35_AIPRE_IIR_EN | ISP35_AIPRE_GAIN_EN |
ISP35_AIPRE_IIR2DDR_EN | ISP35_AIPRE_GIAN2DDR_EN);
val |= ISP35_AIPRE_ITS_FORCE_UPD;
rkisp_write(dev, ISP35_AI_CTRL, val, false);
val &= ~ISP35_AIPRE_ITS_FORCE_UPD;
rkisp_write(dev, ISP35_AI_CTRL, val, false);
dev->irq_f_ends_mask &= ~ISP_FRAME_VPSL;
/* fix isp_fe awbgain to 1x */
writel(0x01000100, hw->base_addr + ISP3X_ISP_AWB_GAIN0_G);
writel(0x01000100, hw->base_addr + ISP3X_ISP_AWB_GAIN0_RB);
writel(0x01000100, hw->base_addr + ISP3X_ISP_AWB_GAIN1_G);
writel(0x01000100, hw->base_addr + ISP3X_ISP_AWB_GAIN1_RB);
/* fix isp_fe ob to 0 */
writel(0, hw->base_addr + ISP3X_BLS_A_FIXED);
writel(0, hw->base_addr + ISP3X_BLS_B_FIXED);
writel(0, hw->base_addr + ISP3X_BLS_C_FIXED);
writel(0, hw->base_addr + ISP3X_BLS_D_FIXED);
writel(0, hw->base_addr + ISP32_BLS_ISP_OB_OFFSET);
val = rkisp_read_reg_cache(dev, ISP32_BLS_ISP_OB_OFFSET);
val &= 0xffff0000;
writel(val, hw->base_addr + ISP32_BLS_ISP_OB_OFFSET);
/* update bay3d buf */
val = priv->bay3d_iir_stride;
writel(val, hw->base_addr + ISP3X_MI_DBR_RD_LENGTH);
val = priv->buf_bay3d_iir_l2.dma_addr;
writel(val, hw->base_addr + ISP39_AIISP_RD_BASE);
writel(val, hw->base_addr + ISP3X_MI_BAY3D_IIR_WR_BASE);
writel(val, hw->base_addr + ISP3X_MI_BAY3D_IIR_RD_BASE);
val = priv->buf_bay3d_ds_l2.dma_addr;
writel(val, hw->base_addr + ISP3X_MI_BAY3D_DS_WR_BASE);
writel(val, hw->base_addr + ISP3X_MI_BAY3D_DS_RD_BASE);
val = priv->buf_bay3d_wgt_l2.dma_addr;
writel(val, hw->base_addr + ISP3X_MI_BAY3D_CUR_WR_BASE);
writel(val, hw->base_addr + ISP3X_MI_BAY3D_CUR_RD_BASE);
val = rkisp_read(dev, MI_WR_CTRL2, true);
val |= ISP3X_BAY3D_IIRSELF_UPD | ISP3X_BAY3D_CURSELF_UPD |
ISP3X_BAY3D_DSSELF_UPD | ISP3X_BAY3D_RDSELF_UPD |
ISP3X_DBR_RDSELF_UPD;
writel(val, hw->base_addr + MI_WR_CTRL2);
/* update rawrd buf */
val = rkisp_read_reg_cache(dev, ISP39_AIISP_RD_BASE);
writel(val, hw->base_addr + ISP3X_MI_RAWS_RD_BASE);
val = rkisp_read_reg_cache(dev, ISP3X_CSI2RX_RAW_RD_CTRL);
val &= ~(ISP3X_CSI_RAW_RD_ALIGN | ISP35_RX0_FORCE_UPD);
val |= ISP35_RXS_FORCE_UPD | ISP3X_CSI_RAW_RD_UNCOMPACT;
writel(val, hw->base_addr + ISP3X_CSI2RX_RAW_RD_CTRL);
rkisp_write(dev, CSI2RX_CTRL0, SW_IBUF_OP_MODE(HDR_RDBK_FRAME1) | SW_CSI2RX_EN, true);
}
static void
rkisp_params_aiisp_l2_exit_v35(struct rkisp_isp_params_vdev *params_vdev)
{
struct rkisp_device *dev = params_vdev->dev;
struct rkisp_hw_dev *hw = dev->hw_dev;
struct rkisp_stream *stream;
u32 val;
/* restore rawrx */
if (IS_HDR_RDBK(dev->rd_mode)) {
stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
stream->ops->config_mi(stream);
val = rkisp_read_reg_cache(dev, ISP3X_MI_RAWS_RD_BASE);
rkisp_write(dev, ISP3X_MI_RAWS_RD_BASE, val, false);
}
/* enable aipre and vpsl output */
val = rkisp_read(dev, ISP35_AI_CTRL, false);
val &= ~ISP35_AIISP_ST;
val |= ISP35_AIPRE_GIAN2DDR_EN | ISP35_AIISP_EN |
ISP35_AIPRE_IIR_EN | ISP35_AIPRE_GAIN_EN |
ISP35_AIISP_RAW12_MSB | ISP35_AIPRE_ITS_FORCE_UPD;
rkisp_write(dev, ISP35_AI_CTRL, val, false);
val &= ~ISP35_AIPRE_ITS_FORCE_UPD;
rkisp_write(dev, ISP35_AI_CTRL, val, false);
dev->irq_f_ends_mask |= ISP_FRAME_VPSL;
/* restore isp_fe awbgain */
val = rkisp_read_reg_cache(dev, ISP3X_ISP_AWB_GAIN0_G);
rkisp_write(dev, ISP3X_ISP_AWB_GAIN0_G, val, false);
val = rkisp_read_reg_cache(dev, ISP3X_ISP_AWB_GAIN0_RB);
rkisp_write(dev, ISP3X_ISP_AWB_GAIN0_RB, val, false);
val = rkisp_read_reg_cache(dev, ISP3X_ISP_AWB_GAIN1_G);
rkisp_write(dev, ISP3X_ISP_AWB_GAIN1_G, val, false);
val = rkisp_read_reg_cache(dev, ISP3X_ISP_AWB_GAIN1_RB);
rkisp_write(dev, ISP3X_ISP_AWB_GAIN1_RB, val, false);
/* restore isp_fe ob */
val = rkisp_read_reg_cache(dev, ISP3X_BLS_A_FIXED);
rkisp_write(dev, ISP3X_BLS_A_FIXED, val, false);
val = rkisp_read_reg_cache(dev, ISP3X_BLS_B_FIXED);
rkisp_write(dev, ISP3X_BLS_B_FIXED, val, false);
val = rkisp_read_reg_cache(dev, ISP3X_BLS_C_FIXED);
rkisp_write(dev, ISP3X_BLS_C_FIXED, val, false);
val = rkisp_read_reg_cache(dev, ISP3X_BLS_D_FIXED);
rkisp_write(dev, ISP3X_BLS_D_FIXED, val, false);
val = rkisp_read_reg_cache(dev, ISP32_BLS_ISP_OB_OFFSET);
rkisp_write(dev, ISP32_BLS_ISP_OB_OFFSET, val, false);
/* update bay3d buf */
val = rkisp_read_reg_cache(dev, ISP3X_MI_DBR_RD_LENGTH);
rkisp_write(dev, ISP3X_MI_DBR_RD_LENGTH, val, false);
val = rkisp_read_reg_cache(dev, ISP39_AIISP_RD_BASE);
rkisp_write(dev, ISP39_AIISP_RD_BASE, val, false);
val = rkisp_read_reg_cache(dev, ISP3X_MI_BAY3D_IIR_WR_BASE);
rkisp_write(dev, ISP3X_MI_BAY3D_IIR_WR_BASE, val, false);
val = rkisp_read_reg_cache(dev, ISP3X_MI_BAY3D_IIR_RD_BASE);
rkisp_write(dev, ISP3X_MI_BAY3D_IIR_RD_BASE, val, false);
val = rkisp_read_reg_cache(dev, ISP3X_MI_BAY3D_DS_WR_BASE);
rkisp_write(dev, ISP3X_MI_BAY3D_DS_WR_BASE, val, false);
val = rkisp_read_reg_cache(dev, ISP3X_MI_BAY3D_DS_RD_BASE);
rkisp_write(dev, ISP3X_MI_BAY3D_DS_RD_BASE, val, false);
val = rkisp_read_reg_cache(dev, ISP3X_MI_BAY3D_CUR_WR_BASE);
rkisp_write(dev, ISP3X_MI_BAY3D_CUR_WR_BASE, val, false);
val = rkisp_read_reg_cache(dev, ISP3X_MI_BAY3D_CUR_RD_BASE);
rkisp_write(dev, ISP3X_MI_BAY3D_CUR_RD_BASE, val, false);
if (hw->is_single) {
val = rkisp_read(dev, MI_WR_CTRL2, true);
val |= ISP3X_BAY3D_IIRSELF_UPD | ISP3X_BAY3D_CURSELF_UPD |
ISP3X_BAY3D_DSSELF_UPD | ISP3X_BAY3D_RDSELF_UPD |
ISP3X_DBR_RDSELF_UPD;
writel(val, hw->base_addr + MI_WR_CTRL2);
}
if (!IS_HDR_RDBK(dev->rd_mode)) {
rkisp_clear_bits(dev, ISP33_BAY3D_CTRL0, 0xffff0002, false);
rkisp_params_cfg_v35(params_vdev, dev->aiisp_fe_seq + 1, RKISP_PARAMS_IMD);
rkisp_write(dev, CSI2RX_CTRL0, SW_IBUF_OP_MODE(dev->rd_mode), true);
}
dev->is_aiisp_l2_st = false;
}
static struct rkisp_isp_params_ops rkisp_isp_params_ops_tbl = {
@@ -6545,6 +6793,8 @@ static struct rkisp_isp_params_ops rkisp_isp_params_ops_tbl = {
.aiisp_start = rkisp_params_aiisp_start_v35,
.vpsl_update_regs = rkisp_vpsl_update_regs_v35,
.aiisp_switch = rkisp_params_aiisp_switch_v35,
.aiisp_l2_enter = rkisp_params_aiisp_l2_enter_v35,
.aiisp_l2_exit = rkisp_params_aiisp_l2_exit_v35,
};
int rkisp_init_params_vdev_v35(struct rkisp_isp_params_vdev *params_vdev)
@@ -8806,6 +9056,9 @@ static void rkisp_get_params_bay3d(struct rkisp_isp_params_vdev *params_vdev,
arg->btnr_ldc_wrap_ext_bound_offset = val & 0xffff;
arg->btnr_ldcltp_mode = !!(val & BIT(16));
val = isp3_param_read(params_vdev, ISP35_B3DLDC_FFFF_OFF, 0);
arg->b3dldc_last = val & 0x1ff;
val = priv->buf_b3dldc_idx[0];
arg->lut_buf_fd = priv->buf_b3dldc[0][val].dma_fd;
}

8
drivers/media/platform/rockchip/isp/isp_params_v35.h
View File

@@ -38,6 +38,10 @@ struct rkisp_isp_params_val_v35 {
struct rkisp_dummy_buffer buf_vpsl[RKISP_BUFFER_MAX];
struct rkisp_dummy_buffer buf_y_src[RKISP_BUFFER_MAX];
struct rkisp_dummy_buffer buf_bay3d_iir_l2;
struct rkisp_dummy_buffer buf_bay3d_wgt_l2;
struct rkisp_dummy_buffer buf_bay3d_ds_l2;
spinlock_t buf_lock;
struct list_head iir_list;
struct list_head gain_list;
@@ -53,7 +57,8 @@ struct rkisp_isp_params_val_v35 {
struct rkisp_dummy_buffer *pbuf_y_src;
u32 bay3d_iir_rw_fmt;
u32 bay3d_iir_offs;
u32 bay3d_iir_pk_offs;
u32 bay3d_iir_pk_stride;
u32 bay3d_iir_stride;
u32 bay3d_iir_size;
int bay3d_iir_cnt;
@@ -105,6 +110,7 @@ struct rkisp_isp_params_val_v35 {
bool is_af_fe;
bool is_awb_fe;
bool is_aiawb_fe;
bool is_aiisp_l2_buf;
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35)

4
drivers/media/platform/rockchip/isp/isp_stats_v35.c
View File

@@ -464,6 +464,10 @@ rkisp_stats_send_meas_fe(struct rkisp_isp_stats_vdev *stats_vdev)
isp3_module_done(stats_vdev, ISP3X_RAWHIST_BIG1_BASE, val);
}
}
if (dev->is_aiisp_l2_st)
return;
rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, &ns, true);
if (!ns)
ns = ktime_get_ns();

30
drivers/media/platform/rockchip/isp/procfs.c
View File

@@ -1189,23 +1189,28 @@ static void isp35_show(struct rkisp_device *dev, struct seq_file *p)
val, dev->hdr_wrap_line);
val = rkisp_read(dev, ISP33_BAY3D_CTRL0, false);
tmp = rkisp_read(dev, ISP33_BAY3D_CTRL2, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d iir_rw_fmt:%d b3dldch:0x%x b3dldcv:0x%x\n"
seq_printf(p, "%-10s %s(0x%x) bypass:%d iir_rw_fmt:%d\n"
"\t b3dldch:0x%x map_err:%d b3dldcv:0x%x map_err:%d\n"
"\t lp_en(me_off:%d gic:%d bf:%d avg:%d) size(iir:%d ds:%d wgt:%d)\n",
"BAY3D", (val & 1) ? "ON" : "OFF", val, !!(val & BIT(1)), (val >> 13) & 0x7,
rkisp_read(dev, ISP35_B3DLDC_ADR_STS, false),
!!(rkisp_read(dev, ISP35_B3DLDC_ADR_STS, true) & BIT(29)),
rkisp_read(dev, ISP35_B3DLDC_CTRL, false),
!!(rkisp_read(dev, ISP35_B3DLDC_CTRL, true) & BIT(12)),
!(val & BIT(8)), !!(tmp & BIT(20)), !!(tmp & BIT(21)), !!(tmp & BIT(22)),
priv->buf_bay3d_iir[0].size, priv->buf_bay3d_ds[0].size, priv->buf_bay3d_wgt[0].size);
val = rkisp_read(dev, ISP35_AI_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) vpsl(ctrl:0x%x chn:0x%x), aiisp(idx:%d cnt:%d)\n"
"\t iir(idx:%d cnt:%d) gain(idx:%d cnt:%d) aipre(idx:%d cnt:%d) vpsl(idx:%d cnt:%d)\n",
seq_printf(p, "%-10s %s(0x%x) vpsl(ctrl:0x%x chn:0x%x), l2(%d cnt:%d)\n"
"\t aiisp_output(idx:%d cnt:%d size:%d) iir(idx:%d cnt:%d size:%d)\n"
"\t gain(idx:%d cnt:%d size:%d) aipre(idx:%d cnt:%d size:%d) vpsl(idx:%d cnt:%d size:%d)\n",
"AINR", (val & 1) ? "ON" : "OFF", val,
vpsl_read(dev, VPSL_PYR_CTRL, false), vpsl_read(dev, VPSL_PYR_CHN, false),
priv->aiisp_cur_idx, priv->aiisp_cnt,
priv->bay3d_iir_cur_idx, priv->bay3d_iir_cnt,
priv->gain_cur_idx, priv->gain_cnt,
priv->aipre_gain_cur_idx, priv->aipre_gain_cnt,
priv->vpsl_cur_idx, priv->vpsl_cnt);
dev->is_aiisp_l2, priv->is_aiisp_l2_buf,
priv->aiisp_cur_idx, priv->aiisp_cnt, priv->buf_aiisp[0].size,
priv->bay3d_iir_cur_idx, priv->bay3d_iir_cnt, priv->buf_bay3d_iir[0].size,
priv->gain_cur_idx, priv->gain_cnt, priv->buf_gain[0].size,
priv->aipre_gain_cur_idx, priv->aipre_gain_cnt, priv->buf_aipre_gain[0].size,
priv->vpsl_cur_idx, priv->vpsl_cnt, priv->buf_vpsl[0].size);
val = rkisp_read(dev, ISP3X_YNR_GLOBAL_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) bypass(hi:%d mi:%d lo:%d) lp_en:%d\n", "YNR",
(val & 1) ? "ON" : "OFF", val,
@@ -1362,9 +1367,14 @@ static int isp_show(struct seq_file *p, void *v)
if (!dev->is_aiisp_en)
snprintf(info, sizeof(info), "time:%dms", sdev->dbg.interval / 1000 / 1000);
else
else if (!dev->is_aiisp_l2)
snprintf(info, sizeof(info), "time(fe:%dms be:%dms)",
sdev->dbg.interval / 1000 / 1000, sdev->dbg.interval_be / 1000 / 1000);
sdev->dbg.interval / 1000 / 1000, sdev->dbg_be.interval / 1000 / 1000);
else
snprintf(info, sizeof(info), "time(fe:%dms fe_l2:%dms be:%dms)",
sdev->dbg.interval / 1000 / 1000,
sdev->dbg_l2.interval / 1000 / 1000,
sdev->dbg_be.interval / 1000 / 1000);
if (IS_HDR_RDBK(dev->hdr.op_mode)) {
stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
seq_printf(p, "%-10s mode:frame%d (frame:%d rate:%dms state:%s %s frameloss:%d)"

3
drivers/media/platform/rockchip/isp/regs_v3x.h
View File

@@ -2090,6 +2090,7 @@
#define ISP35_B3DLDC_CTRL (ISP3X_LDCH_BASE + 0x00080)
#define ISP35_B3DLDC_WR_ADDR (ISP3X_LDCH_BASE + 0x000a8)
#define ISP35_B3DLDC_WR_STRIDE (ISP3X_LDCH_BASE + 0x000ac)
#define ISP35_B3DLDC_FFFF_OFF (ISP3X_LDCH_BASE + 0x000b0)
#define ISP35_B3DLDC_ADR_STS (ISP3X_LDCH_BASE + 0x000e0)
#define ISP35_B3DLDC_EXTBOUND1 (ISP3X_LDCH_BASE + 0x000e8)
@@ -3164,6 +3165,8 @@
#define ISP3X_RXSELF_FORCE_UPD BIT(31)
#define ISP35_RXS_FORCE_UPD BIT(31)
#define ISP35_RX0_FORCE_UPD BIT(30)
#define ISP3X_CSI_RAW_RD_UNCOMPACT BIT(3)
#define ISP3X_CSI_RAW_RD_ALIGN BIT(4)
/* DEBAYER */

233
drivers/media/platform/rockchip/isp/rkisp.c
View File

@@ -89,6 +89,7 @@ static void rkisp_config_aiisp(struct rkisp_device *dev);
static void rkisp_config_fpn(struct rkisp_device *dev);
static void rkisp_dvbm_start_event(struct rkisp_device *dev);
static int rkisp_rdbk_aiisp_event(struct rkisp_device *dev, u32 cmd, void *arg);
static void rkisp_aiisp_l2(struct rkisp_device *dev, bool on, bool is_hw_link);
static inline struct rkisp_device *sd_to_isp_dev(struct v4l2_subdev *sd)
{
@@ -679,23 +680,21 @@ static void rkisp_update_list_reg(struct rkisp_device *dev)
writel(val, hw->base_addr + MI_WR_CTRL2);
rkisp_update_regs(dev, ISP35_AIAWB_CTRL1, ISP35_AIAWB_WR_BASE_VIR);
val = rkisp_read(dev, ISP35_AIAWB_CTRL0, false);
if (val & ISP35_AIAWB_EN) {
val |= ISP35_AIAWB_SELF_UPD;
writel(val, hw->base_addr + ISP35_AIAWB_CTRL0);
}
val |= ISP35_AIAWB_SELF_UPD;
writel(val, hw->base_addr + ISP35_AIAWB_CTRL0);
if (rkisp_read(dev, ISP39_W3A_CTRL0, false) & ISP39_W3A_EN) {
val = rkisp_read(dev, ISP3X_SWS_CFG, false);
val |= ISP3X_3A_DDR_WRITE_EN;
writel(val, hw->base_addr + ISP3X_SWS_CFG);
}
val = rkisp_read(dev, ISP35_AI_CTRL, false);
if (val & ISP35_AIISP_EN) {
val &= ~ISP35_AIISP_ST;
val |= ISP35_AIPRE_ITS_FORCE_UPD;
writel(val, hw->base_addr + ISP35_AI_CTRL);
val &= ~ISP35_AIPRE_ITS_FORCE_UPD;
writel(val, hw->base_addr + ISP35_AI_CTRL);
}
val &= ~ISP35_AIISP_ST;
val |= ISP35_AIPRE_ITS_FORCE_UPD;
writel(val, hw->base_addr + ISP35_AI_CTRL);
val &= ~ISP35_AIPRE_ITS_FORCE_UPD;
writel(val, hw->base_addr + ISP35_AI_CTRL);
dev->params_vdev.ops->vpsl_update_regs(&dev->params_vdev);
}
if (dev->isp_ver >= ISP_V33) {
@@ -837,12 +836,12 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
rkisp_params_cfg(params_vdev, cur_frame_id, RKISP_PARAMS_IMD);
rkisp_config_cmsk(dev);
if (!dev->is_aiisp_en ||
(dev->is_aiisp_sync && !dev->is_first_frame))
(dev->is_aiisp_sync && !dev->is_aiisp_l2 && !dev->is_aiisp_first_frame))
rkisp_stream_frame_start(dev, 0);
}
if (!dev->is_aiisp_en ||
(dev->is_aiisp_sync && !dev->is_first_frame))
(dev->is_aiisp_sync && !dev->is_aiisp_l2 && !dev->is_aiisp_first_frame))
rkisp_sditf_sof(dev, 0);
if (!hw->is_single) {
@@ -871,7 +870,7 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
run_next:
if (!dev->sw_rd_cnt &&
(!dev->is_aiisp_en ||
(dev->is_aiisp_sync && !dev->is_first_frame)))
(dev->is_aiisp_sync && !dev->is_aiisp_l2 && !dev->is_aiisp_first_frame)))
rkisp_rockit_frame_start(dev);
rkisp_params_cfgsram(params_vdev, true, false);
stats_vdev->rdbk_drop = false;
@@ -983,7 +982,7 @@ run_next:
rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 1, true);
if (!dev->is_aiisp_en ||
(dev->is_aiisp_sync && !dev->is_first_frame))
(dev->is_aiisp_sync && !dev->is_aiisp_l2 && !dev->is_aiisp_first_frame))
rkisp_check_mi_ends_mask(dev);
if (hw->is_frm_buf) {
@@ -1018,7 +1017,9 @@ run_next:
cur_frame_id, dma2frm + 1, val, is_try);
if (!hw->is_shutdown) {
rkisp_unite_write(dev, CSI2RX_CTRL0, val, true);
if (dev->is_aiisp_en && dev->is_aiisp_sync && !dev->is_first_frame) {
if (dev->is_aiisp_en && dev->is_aiisp_sync &&
!dev->is_aiisp_l2 && !dev->is_aiisp_first_frame) {
/* isp FE(fn) and BE(fn-1) start read together for aiisp L1 */
dev->irq_ends_mask |= ISP_FRAME_END;
if (dev->isp_ver == ISP_V39) {
val = rkisp_read(dev, ISP3X_MI_RD_CTRL2, false);
@@ -1074,6 +1075,8 @@ void rkisp_vicap_hw_link(struct rkisp_device *dev, int on)
{
struct v4l2_subdev *sd = dev->active_sensor->sd;
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"%s on:%d\n", __func__, on);
v4l2_subdev_call(sd, core, ioctl, RKISP_VICAP_CMD_HW_LINK, &on);
}
@@ -1157,7 +1160,7 @@ static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd)
/* wait 2 frame to start isp for fast */
if (isp->is_rtt_first && max == 1 && isp->is_first_frame)
goto end;
if (isp->is_aiisp_sync && !isp->is_first_frame) {
if (isp->is_aiisp_sync && !isp->is_aiisp_first_frame) {
rkisp_rdbk_aiisp_event(isp, T_CMD_LEN, &len[id]);
if (len[id])
is_aiisp_ready = true;
@@ -1432,13 +1435,31 @@ static void rkisp_back_end_idle(struct rkisp_device *dev)
rkisp_rdbk_aiisp_event(dev, T_CMD_END, NULL);
if (dev->isp_state == ISP_STOP && dev->hw_dev->is_idle)
wake_up(&dev->sync_onoff);
if (dev->is_aiisp_stopping && dev->hw_dev->is_be_idle &&
dev->aiisp_stop_seq == dev->dmarx_dev.cur_be_frame.id) {
if (dev->is_aiisp_l2_st)
rkisp_aiisp_l2(dev, false, true);
if (dev->is_aiisp_stopping && dev->hw_dev->is_be_idle) {
struct rkisp_aiisp_st st = { 0 };
unsigned long lock_flags = 0;
int len = 0;
dev->is_aiisp_en = false;
dev->is_aiisp_stop = true;
dev->is_aiisp_stopping = false;
/* clear aiisp list */
spin_lock_irqsave(&dev->hw_dev->rdbk_lock, lock_flags);
rkisp_rdbk_aiisp_event(dev, T_CMD_LEN, &len);
if (len) {
rkisp_rdbk_aiisp_event(dev, T_CMD_DEQUEUE, &st);
dev->dmarx_dev.cur_be_frame.id = st.sequence;
dev->dmarx_dev.cur_be_frame.timestamp = st.timestamp;
dev->hw_dev->cur_be_dev_id = dev->dev_id;
dev->hw_dev->is_be_idle = false;
}
spin_unlock_irqrestore(&dev->hw_dev->rdbk_lock, lock_flags);
if (len)
rkisp_params_aiisp_start(&dev->params_vdev, &st);
if (dev->params_vdev.ops->aiisp_switch)
dev->params_vdev.ops->aiisp_switch(&dev->params_vdev, false);
dev->is_aiisp_stopping = false;
dev->is_aiisp_stop = true;
rkisp_vicap_hw_link(dev, true);
}
}
@@ -1454,7 +1475,7 @@ void rkisp_check_idle(struct rkisp_device *dev, u32 irq)
spin_lock_irqsave(&hw->rdbk_lock, lock_flags);
dev->irq_ends |= (irq & dev->irq_ends_mask);
dev->irq_f_ends |= (irq & dev->irq_f_ends_mask);
v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"%s irq:0x%x (0x%x 0x%x) (0x%x 0x%x)\n",
__func__, irq,
dev->irq_f_ends, dev->irq_f_ends_mask,
@@ -1478,7 +1499,10 @@ void rkisp_check_idle(struct rkisp_device *dev, u32 irq)
if (isp_front_end) {
if (hw->is_single && !IS_HDR_RDBK(dev->rd_mode)) {
rkisp_config_aiisp(dev);
if (!dev->is_aiisp_l2_st)
rkisp_config_aiisp(dev);
if (dev->is_aiisp_l2)
rkisp_aiisp_l2(dev, true, true);
return;
}
rkisp_front_end_idle(dev);
@@ -2118,7 +2142,7 @@ static int rkisp_config_isp(struct rkisp_device *dev)
irq_mask |= CIF_ISP_FRAME_IN;
if (dev->is_aiisp_en)
irq_mask |= ISP3X_BAY3D_FRM_END;
rkisp_unite_set_bits(dev, CIF_ISP_IMSC, 0, irq_mask, true);
rkisp_unite_set_bits(dev, CIF_ISP_IMSC, 0, irq_mask, false);
if ((dev->isp_ver == ISP_V20 ||
dev->isp_ver == ISP_V21) &&
@@ -2551,6 +2575,7 @@ static int rkisp_isp_start(struct rkisp_device *dev)
else if (dev->is_aiisp_en)
dev->irq_ends_mask = ISP_FRAME_BNR;
dev->irq_ends = 0;
dev->is_aiisp_first_frame = dev->is_aiisp_en;
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"%s MI_CTRL 0x%08x ISP_CTRL 0x%08x\n", __func__,
@@ -3833,6 +3858,9 @@ rkisp_isp_queue_event_sof(struct rkisp_device *dev)
u64 ns = rkisp_time_get_ns(dev);
u32 seq;
if (dev->is_aiisp_l2_st)
return;
spin_lock_irqsave(&dev->rdbk_lock, flag);
seq = ++dev->dmarx_dev.cur_frame.id;
dev->dmarx_dev.cur_frame.timestamp = ns;
@@ -4003,6 +4031,12 @@ static void rkisp_config_aiisp(struct rkisp_device *dev)
} else if (!dev->is_aiisp_en && dev->aiisp_cfg.mode) {
dev->is_aiisp_en = true;
dev->is_aiisp_stop = false;
dev->is_aiisp_l2 = false;
if (dev->aiisp_cfg.mode == 2) {
dev->is_aiisp_l2 = true;
dev->is_aiisp_l2_init = true;
dev->is_aiisp_l2_first_cfg = true;
}
if (dev->params_vdev.ops->aiisp_switch)
dev->params_vdev.ops->aiisp_switch(&dev->params_vdev, true);
if (!dev->hw_dev->is_single || IS_HDR_RDBK(dev->rd_mode))
@@ -4012,7 +4046,7 @@ static void rkisp_config_aiisp(struct rkisp_device *dev)
if (dev->is_aiisp_en) {
irq |= ISP3X_BAY3D_FRM_END;
if (!dev->is_aiisp_sync)
dev->irq_f_ends_mask |= ISP_FRAME_BNR;
dev->irq_f_ends_mask |= ISP_FRAME_BNR | ISP_FRAME_VPSL;
en = (dev->isp_ver == ISP_V39) ? ISP39_AIISP_EN : ISP35_AIISP_EN;
}
irq_mask = ISP39_AIISP_LINECNT_DONE | ISP3X_OUT_FRM_QUARTER | ISP3X_BAY3D_FRM_END;
@@ -4049,32 +4083,26 @@ static int rkisp_set_aiisp_linecnt(struct rkisp_device *dev,
struct rkisp_aiisp_cfg *cfg)
{
unsigned long lock_flags = 0;
int ret = -EINVAL;
if (dev->isp_ver != ISP_V39 && dev->isp_ver != ISP_V35)
return ret;
return -EINVAL;
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"%s mode:%d wr:%d rd:%d wr_mode:%d\n", __func__,
cfg->mode, cfg->wr_linecnt, cfg->rd_linecnt, cfg->wr_mode);
spin_lock_irqsave(&dev->aiisp_lock, lock_flags);
if (!(dev->isp_state & ISP_START)) {
if (!cfg->mode && cfg->wr_linecnt && cfg->rd_linecnt) {
/* TODO support multi-sensor */
if (!dev->hw_dev->is_single) {
dev_err(dev->dev,
"aibnr no support dynamic switch for multi-sensor now\n");
goto unlock;
}
if (!cfg->mode && cfg->wr_linecnt && cfg->rd_linecnt)
dev->is_aiisp_stop = true;
}
dev->is_aiisp_en = !!cfg->mode;
}
/* TODO support l2 for multi-sensor */
if (!dev->hw_dev->is_single && cfg->mode == 2)
cfg->mode = 1;
dev->is_aiisp_upd = true;
dev->aiisp_cfg = *cfg;
ret = 0;
unlock:
spin_unlock_irqrestore(&dev->aiisp_lock, lock_flags);
return ret;
return 0;
}
static int rkisp_get_aiisp_linecnt(struct rkisp_device *dev,
@@ -4098,6 +4126,28 @@ static void rkisp_aiisp_irq_event(struct rkisp_device *dev, u32 irq)
rkisp_params_aiisp_event(&dev->params_vdev, irq);
}
static void rkisp_rdbk_aiisp_start(struct rkisp_device *dev)
{
u32 reg, val;
rkisp_stream_frame_start(dev, 0);
rkisp_dvbm_start_event(dev);
rkisp_rockit_frame_start(dev);
rkisp_sditf_sof(dev, 0);
rkisp_check_mi_ends_mask(dev);
if (dev->isp_ver == ISP_V39) {
reg = ISP3X_MI_RD_CTRL2;
val = rkisp_read(dev, reg, false);
val |= ISP39_AIISP_ST;
} else {
reg = ISP35_AI_CTRL;
val = rkisp_read(dev, reg, false);
val |= ISP35_AIISP_ST;
}
writel(val, dev->hw_dev->base_addr + reg);
}
static int rkisp_rdbk_aiisp_handle(struct rkisp_device *dev, u32 cmd)
{
struct rkisp_hw_dev *hw = dev->hw_dev;
@@ -4108,7 +4158,7 @@ static int rkisp_rdbk_aiisp_handle(struct rkisp_device *dev, u32 cmd)
spin_lock_irqsave(&hw->rdbk_lock, lock_flags);
if (cmd == T_CMD_END) {
hw->is_be_idle = true;
if (dev->is_aiisp_sync)
if (dev->is_aiisp_sync || dev->is_aiisp_l2)
goto end;
}
if (hw->is_shutdown)
@@ -4134,20 +4184,10 @@ static int rkisp_rdbk_aiisp_handle(struct rkisp_device *dev, u32 cmd)
end:
spin_unlock_irqrestore(&hw->rdbk_lock, lock_flags);
if (len) {
dev->isp_sdev.dbg.timestamp_be = rkisp_time_get_ns(dev);
dev->isp_sdev.dbg_be.timestamp = rkisp_time_get_ns(dev);
ret = rkisp_params_aiisp_start(&dev->params_vdev, &st);
if (ret == 0 && !dev->is_aiisp_sync) {
rkisp_stream_frame_start(dev, 0);
rkisp_dvbm_start_event(dev);
rkisp_rockit_frame_start(dev);
rkisp_sditf_sof(dev, 0);
rkisp_check_mi_ends_mask(dev);
if (dev->isp_ver == ISP_V39)
rkisp_set_bits(dev, ISP3X_MI_RD_CTRL2, 0, ISP39_AIISP_ST, true);
else
rkisp_set_bits(dev, ISP35_AI_CTRL, 0, ISP35_AIISP_ST, true);
}
if (ret == 0 && !dev->is_aiisp_sync)
rkisp_rdbk_aiisp_start(dev);
}
return ret;
}
@@ -4156,13 +4196,14 @@ static int rkisp_rdbk_aiisp_event(struct rkisp_device *dev, u32 cmd, void *arg)
{
struct kfifo *fifo = &dev->rdbk_be_kfifo;
unsigned long lock_flags = 0;
struct rkisp_aiisp_st *st;
int val, ret = 0;
if (dev->is_aiisp_yuv && cmd == T_CMD_QUEUE) {
struct rkisp_stream *stream = &dev->cap_dev.stream[RKISP_STREAM_MP];
struct rkisp_aiisp_st *st = arg;
v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
st = arg;
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"aiisp yuv input seq:%d idx(vpsl:%d aipre:%d ysrc:%d ydst:%d)\n",
st->sequence, st->vpsl_index, st->aipre_gain_index,
st->y_src_index, st->y_dest_index);
@@ -4178,6 +4219,9 @@ static int rkisp_rdbk_aiisp_event(struct rkisp_device *dev, u32 cmd, void *arg)
case T_CMD_QUEUE:
if (!arg)
break;
st = arg;
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"aiisp input seq:%d\n", st->sequence);
if (!kfifo_is_full(fifo))
kfifo_in(fifo, arg, sizeof(struct rkisp_aiisp_st));
else
@@ -4198,10 +4242,14 @@ static int rkisp_rdbk_aiisp_event(struct rkisp_device *dev, u32 cmd, void *arg)
}
spin_unlock_irqrestore(&dev->rdbk_lock, lock_flags);
if (dev->is_aiisp_en && dev->is_aiisp_sync &&
arg && cmd == T_CMD_QUEUE) {
if (dev->hw_dev->is_idle)
if (dev->is_aiisp_en && arg && cmd == T_CMD_QUEUE &&
(dev->is_aiisp_sync || dev->is_aiisp_l2)) {
if (!dev->is_aiisp_l2 && dev->hw_dev->is_idle) {
rkisp_rdbk_trigger_event(dev, T_CMD_QUEUE, NULL);
} else if (dev->is_aiisp_l2 && dev->is_aiisp_l2_waiting) {
dev->is_aiisp_l2_waiting = false;
rkisp_aiisp_l2(dev, true, false);
}
goto end;
}
if (cmd == T_CMD_QUEUE || cmd == T_CMD_END)
@@ -4210,6 +4258,52 @@ end:
return ret;
}
/* Fn->isp_fe->aiisp->raw(fn)->isp_fe->isp_be->output */
static void rkisp_aiisp_l2(struct rkisp_device *dev, bool on, bool is_hw_link)
{
struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev;
struct rkisp_aiisp_st st = { 0 };
unsigned long lock_flags = 0;
int len = 0;
if (!on) {
if (params_vdev->ops->aiisp_l2_exit)
params_vdev->ops->aiisp_l2_exit(params_vdev);
if (!IS_HDR_RDBK(dev->rd_mode) && !dev->is_aiisp_stopping)
rkisp_vicap_hw_link(dev, true);
return;
}
if (params_vdev->ops->aiisp_l2_enter) {
if (dev->is_aiisp_l2_st) {
dev->isp_sdev.dbg_be.timestamp = rkisp_time_get_ns(dev);
rkisp_aiisp_irq_event(dev, ISP3X_OUT_FRM_QUARTER);
rkisp_rdbk_aiisp_start(dev);
return;
}
dev->isp_sdev.dbg_l2.timestamp = rkisp_time_get_ns(dev);
spin_lock_irqsave(&dev->hw_dev->rdbk_lock, lock_flags);
rkisp_rdbk_aiisp_event(dev, T_CMD_LEN, &len);
if (len) {
rkisp_rdbk_aiisp_event(dev, T_CMD_DEQUEUE, &st);
dev->dmarx_dev.cur_be_frame.id = st.sequence;
dev->dmarx_dev.cur_be_frame.timestamp = st.timestamp;
dev->hw_dev->cur_be_dev_id = dev->dev_id;
dev->hw_dev->is_be_idle = false;
} else if (!dev->is_aiisp_l2_init) {
dev->is_aiisp_l2_waiting = true;
}
spin_unlock_irqrestore(&dev->hw_dev->rdbk_lock, lock_flags);
if ((len || dev->is_aiisp_l2_waiting) && is_hw_link &&
!IS_HDR_RDBK(dev->rd_mode) && !dev->is_aiisp_stopping)
rkisp_vicap_hw_link(dev, false);
if (len)
params_vdev->ops->aiisp_l2_enter(params_vdev, &st);
if (dev->is_aiisp_l2_init)
dev->is_aiisp_l2_init = false;
}
}
static int rkisp_set_offline_raw_buf_cnt(struct rkisp_device *dev, int *cnt)
{
if (dev->isp_inp & (INP_RAWRD0 | INP_RAWRD2)) {
@@ -5152,7 +5246,7 @@ void rkisp_isp_isr(unsigned int isp_mis,
}
if (!dev->is_aiisp_en ||
(dev->is_aiisp_sync && !dev->is_first_frame))
(dev->is_aiisp_sync && !dev->is_aiisp_first_frame))
rkisp_dvbm_start_event(dev);
dev->is_first_frame = false;
if (IS_HDR_RDBK(dev->hdr.op_mode)) {
@@ -5212,7 +5306,8 @@ vs_skip:
if (isp_mis & ISP39_AIISP_LINECNT_DONE) {
writel(ISP39_AIISP_LINECNT_DONE, base + CIF_ISP_ICR);
rkisp_aiisp_irq_event(dev, ISP39_AIISP_LINECNT_DONE);
if (!dev->is_aiisp_l2_st)
rkisp_aiisp_irq_event(dev, ISP39_AIISP_LINECNT_DONE);
}
if ((isp_mis & (CIF_ISP_DATA_LOSS | CIF_ISP_PIC_SIZE_ERROR))) {
@@ -5283,8 +5378,8 @@ vs_skip:
if (isp_mis & CIF_ISP_FRAME) {
dev->rawaf_irq_cnt = 0;
if (dev->is_aiisp_en)
dev->isp_sdev.dbg.interval_be =
rkisp_time_get_ns(dev) - dev->isp_sdev.dbg.timestamp_be;
dev->isp_sdev.dbg_be.interval =
rkisp_time_get_ns(dev) - dev->isp_sdev.dbg_be.timestamp;
else if (!dev->is_pre_on || !IS_HDR_RDBK(dev->rd_mode))
dev->isp_sdev.dbg.interval =
rkisp_time_get_ns(dev) - dev->isp_sdev.dbg.timestamp;
@@ -5302,7 +5397,7 @@ vs_skip:
rkisp_stream_isp_end(dev, isp_mis);
}
if (isp_mis & CIF_ISP_V_START) {
if (isp_mis & CIF_ISP_V_START && !dev->is_aiisp_l2_st) {
u64 tmp = dev->isp_sdev.dbg.interval + dev->isp_sdev.dbg.timestamp;
dev->isp_sdev.dbg.timestamp = rkisp_time_get_ns(dev);
@@ -5318,14 +5413,20 @@ vs_skip:
if (isp_mis & ISP3X_OUT_FRM_QUARTER) {
writel(ISP3X_OUT_FRM_QUARTER, base + CIF_ISP_ICR);
rkisp_aiisp_irq_event(dev, ISP3X_OUT_FRM_QUARTER);
if (!dev->is_aiisp_l2_st)
rkisp_aiisp_irq_event(dev, ISP3X_OUT_FRM_QUARTER);
}
if (isp_mis & ISP3X_BAY3D_FRM_END) {
writel(ISP3X_BAY3D_FRM_END, base + CIF_ISP_ICR);
if (dev->is_aiisp_en)
dev->isp_sdev.dbg.interval =
rkisp_time_get_ns(dev) - dev->isp_sdev.dbg.timestamp;
if (dev->is_aiisp_en) {
if (!dev->is_aiisp_l2_st)
dev->isp_sdev.dbg.interval = rkisp_time_get_ns(dev) -
dev->isp_sdev.dbg.timestamp;
else
dev->isp_sdev.dbg_l2.interval = rkisp_time_get_ns(dev) -
dev->isp_sdev.dbg_l2.timestamp;
}
rkisp_stats_isr(&dev->stats_vdev, ISP3X_BAY3D_FRM_END, 0);
rkisp_params_isr(&dev->params_vdev, ISP3X_BAY3D_FRM_END);
rkisp_check_idle(dev, ISP_FRAME_BNR);

2
drivers/media/platform/rockchip/isp/rkisp.h
View File

@@ -147,6 +147,8 @@ struct rkisp_isp_subdev {
enum v4l2_quantization quantization;
enum v4l2_colorspace colorspace;
struct frame_debug_info dbg;
struct frame_debug_info dbg_be;
struct frame_debug_info dbg_l2;
};
struct rkisp_emd_data {

77
drivers/mfd/rk808.c
View File

@@ -957,6 +957,12 @@ static int rk817_shutdown_prepare(struct sys_off_data *data)
if (ret)
pr_info("%s:failed to activate pwroff state\n",
__func__);
ret = regmap_update_bits(rk808->regmap,
RK817_SYS_CFG(3),
RK817_SLPPIN_FUNC_MSK,
SLPPIN_DN_FUN);
if (ret)
pr_err("shutdown: config SLPPIN_DN_FUN error!\n");
}
/* pmic sleep shutdown function */
@@ -1173,29 +1179,8 @@ static int rk801_pinctrl_init(struct device *dev, struct rk808 *rk808)
static int rk817_pinctrl_init(struct device *dev, struct rk808 *rk808)
{
int ret;
struct platform_device *pinctrl_dev;
struct pinctrl_state *default_st;
pinctrl_dev = platform_device_alloc("rk805-pinctrl", -1);
if (!pinctrl_dev) {
dev_err(dev, "Alloc pinctrl dev failed!\n");
return -ENOMEM;
}
pinctrl_dev->dev.parent = dev;
ret = platform_device_add(pinctrl_dev);
if (ret) {
platform_device_put(pinctrl_dev);
dev_err(dev, "Add rk805-pinctrl dev failed!\n");
return ret;
}
if (dev->pins && !IS_ERR(dev->pins->p)) {
dev_info(dev, "had get a pinctrl!\n");
return 0;
}
int ret, value;
rk808->pins = devm_kzalloc(dev, sizeof(struct rk808_pin_info),
GFP_KERNEL);
@@ -1244,12 +1229,40 @@ static int rk817_pinctrl_init(struct device *dev, struct rk808 *rk808)
dev_dbg(dev, "no reset-setting pinctrl state\n");
return 0;
}
ret = regmap_update_bits(rk808->regmap,
RK817_SYS_CFG(3),
RK817_SLPPIN_FUNC_MSK,
SLPPIN_NULL_FUN);
if (ret) {
dev_err(dev, "init: config SLPPIN_NULL_FUN error!\n");
return ret;
}
ret = regmap_update_bits(rk808->regmap,
RK817_SYS_CFG(3),
RK817_SLPPOL_MSK,
RK817_SLPPOL_L);
if (ret) {
dev_err(dev, "init: config RK817_SLPPOL_L error!\n");
return ret;
}
/* pmic need the SCL clock to synchronize register */
regmap_read(rk808->regmap, RK817_SYS_STS, &value);
mdelay(2);
ret = pinctrl_select_state(rk808->pins->p, rk808->pins->reset);
if (ret)
dev_dbg(dev, "failed to activate reset-setting pinctrl state\n");
ret = regmap_update_bits(rk808->regmap,
RK817_SYS_CFG(3),
RK817_SLPPIN_FUNC_MSK,
SLPPIN_RST_FUN);
if (ret) {
dev_err(dev, "init: config SLPPIN_RST_FUN error!\n");
return ret;
}
return 0;
}
@@ -1772,6 +1785,15 @@ static int __maybe_unused rk8xx_suspend(struct device *dev)
dev_err(dev, "failed to act slp pinctrl state\n");
return ret;
}
ret = regmap_update_bits(rk808->regmap,
RK817_SYS_CFG(3),
RK817_SLPPIN_FUNC_MSK,
SLPPIN_SLP_FUN);
if (ret) {
dev_err(dev, "suspend: config SLPPIN_SLP_FUN error!\n");
return ret;
}
}
break;
default:
@@ -1827,6 +1849,15 @@ static int __maybe_unused rk8xx_resume(struct device *dev)
ret = pinctrl_select_state(rk808->pins->p, rk808->pins->reset);
if (ret)
dev_dbg(dev, "failed to act reset pinctrl state\n");
ret = regmap_update_bits(rk808->regmap,
RK817_SYS_CFG(3),
RK817_SLPPIN_FUNC_MSK,
SLPPIN_RST_FUN);
if (ret) {
dev_err(dev, "resume: config SLPPIN_RST_FUN error!\n");
return ret;
}
}
break;
default:

17
drivers/rkflash/sfc.c
View File

@@ -93,6 +93,8 @@ int sfc_request(struct rk_sfc_op *op, u32 addr, void *data, u32 size)
union SFCCMD_DATA cmd;
int reg;
int timeout = 0;
u32 *p_data = (u32 *)data;
u32 temp = 0;
reg = readl(g_sfc_reg + SFC_FSR);
@@ -102,6 +104,20 @@ int sfc_request(struct rk_sfc_op *op, u32 addr, void *data, u32 size)
cmd.d32 = op->sfcmd.d32;
if (size && size < 4 && cmd.b.rw == SFC_WRITE) {
if (size == 1)
temp = *((u8 *)data);
else if (size == 2)
temp = *((u16 *)data);
else
temp = ((u8 *)data)[0] | ((u8 *)data)[1] << 8 | ((u8 *)data)[2] << 16;
p_data = &temp;
} else if (size >= 4 && ((uintptr_t)data & 0x3)) {
pr_err("%s data addr unaligned access\n", __func__);
} else if (size & 0x3 && cmd.b.rw == SFC_WRITE) {
pr_err("%s data size unaligned access\n", __func__);
}
if (cmd.b.addrbits == SFC_ADDR_XBITS) {
union SFCCTRL_DATA ctrl;
@@ -158,7 +174,6 @@ int sfc_request(struct rk_sfc_op *op, u32 addr, void *data, u32 size)
} else {
u32 i, words, count, bytes;
union SFCFSR_DATA fifostat;
u32 *p_data = (u32 *)data;
if (cmd.b.rw == SFC_WRITE) {
words = (size + 3) >> 2;

3
include/uapi/linux/rk-aiisp-config.h
View File

@@ -38,6 +38,9 @@
#define RKAIISP_CMD_SET_MEMORY_MODE \
_IOW('V', BASE_VIDIOC_PRIVATE + 6, enum rkaiisp_mem_mode)
#define RKAIISP_CMD_CLEAR_IQPARAMS \
_IO('V', BASE_VIDIOC_PRIVATE + 7)
/**********************EVENT_PRIVATE***************************/
#define RKAIISP_V4L2_EVENT_AIISP_DONE (V4L2_EVENT_PRIVATE_START + 1)

6
include/uapi/linux/rk-isp2-config.h
View File

@@ -331,12 +331,13 @@
#define ISP2X_FBCBUF_FD_NUM 64
#define ISP2X_MESH_BUF_NUM 2
#define ISP2X_MESH_BUF_NUM 3
#define RKISP_BUFFER_MAX 8
struct rkisp_buf_info {
int buf_cnt;
int buf_size;
int buf_stride;
int buf_fd[RKISP_BUFFER_MAX];
} __attribute__ ((packed));
@@ -458,7 +459,7 @@ struct rkisp_aiisp_st {
} __attribute__ ((packed));
/* struct rkisp_aiisp_cfg
* mode: 0:isp whole 1:isp divided into isp_fe and isp_be
* mode: 0:isp whole 1:isp divided into isp_fe and isp_be 2:isp divided into isp_fe and (isp_fe isp_be)
* wr_linecnt: btnr iir write irq line
* rd_linecnt: isp_be read irq line
* wr_mode: 0:frame with only one RKISP_AIISP_WR_LINECNT_ID event, else event per wr_linecnt
@@ -493,6 +494,7 @@ struct rkisp_bnr_buf_info {
__u8 iir_rw_fmt;
__u8 gain_mode;
__u8 yraw_sel;
__u8 aibnr_l2;
/* yraw ds_2x2 to ds_64x64 buf offset and stride */
__u32 vpsl_yraw_offs[VPSL_YRAW_CHN_MAX];
__u32 vpsl_yraw_stride[VPSL_YRAW_CHN_MAX];

4
include/uapi/linux/rk-isp35-config.h
View File

@@ -58,6 +58,7 @@
#define ISP35_MODULE_AI BIT_ULL(51)
#define ISP35_MODULE_AIAWB BIT_ULL(52)
#define ISP35_MODULE_AWBSYNC BIT_ULL(53)
#define ISP35_MODULE_BAY3D_L2 BIT_ULL(54)
#define ISP35_MODULE_FORCE ISP3X_MODULE_FORCE
@@ -603,6 +604,8 @@ struct isp35_bay3d_cfg {
/* B3DLDC_EXTBOUND1 */
__u8 btnr_ldcltp_mode;
__u16 btnr_ldc_wrap_ext_bound_offset;
/* B3DLDC_FFFF_OFF */
__u16 b3dldc_last;
/* lut_ldch:offset data_oft; lut_ldcv:offset data1_oft */
__s32 lut_buf_fd;
} __attribute__ ((packed));
@@ -1722,6 +1725,7 @@ struct isp35_isp_other_cfg {
struct isp35_hdrmge_cfg hdrmge_cfg;
struct isp3x_gain_cfg gain_cfg;
struct isp35_bay3d_cfg bay3d_cfg;
struct isp35_bay3d_cfg bay3d_l2_cfg;
struct isp35_ai_cfg ai_cfg;
struct isp33_cac_cfg cac_cfg;