osd: add viu2 reg write optimize [1/1]

PD#TV-8354 Problem: keystone screen blank probability, viu2 reg write caused blank Solution: add viu2 reg write optimize, update reg that needed Verify: tl1 Change-Id: I17d1cdca2f9dec270ec61bd413b9f9753ab548a8 Signed-off-by: Pengcheng Chen <pengcheng.chen@amlogic.com>
2026-06-10 12:57:06 +09:00 · 2019-08-17 12:46:20 +08:00
parent 5f8c274cbb
commit 678cc4f7b8
7 changed files with 293 additions and 79 deletions
--- a/drivers/amlogic/media/osd/osd.h
+++ b/drivers/amlogic/media/osd/osd.h
@@ -681,6 +681,12 @@ struct hw_debug_s {
 	struct osd_debug_backup_s osd_backup[OSD_BACKUP_COUNT];
 };

+struct viu2_osd_reg_item {
+	u32 addr;
+	u32 val;
+	u32 mask;
+};
+
 struct hw_para_s {
 	struct pandata_s pandata[HW_OSD_COUNT];
 	struct pandata_s dispdata[HW_OSD_COUNT];
@@ -749,7 +755,7 @@ struct hw_para_s {
 	u32 osd_deband_enable;
 	u32 osd_fps[VIU_COUNT];
 	u32 osd_fps_start[VIU_COUNT];
-	u32 osd_display_debug;
+	u32 osd_display_debug[VIU_COUNT];
 	ulong screen_base[HW_OSD_COUNT];
 	ulong screen_size[HW_OSD_COUNT];
 	ulong screen_base_backup[HW_OSD_COUNT];
--- a/drivers/amlogic/media/osd/osd_drm.c
+++ b/drivers/amlogic/media/osd/osd_drm.c
@@ -174,11 +174,13 @@ static ssize_t osd_display_debug_read_file(struct file *file,
 				char __user *userbuf,
 				size_t count, loff_t *ppos)
 {
+	struct seq_file *s = file->private_data;
+	int osd_id = *(int *)s;
 	char buf[128];
 	ssize_t len;
 	u32 osd_display_debug_enable;

-	osd_get_display_debug(&osd_display_debug_enable);
+	osd_get_display_debug(osd_id, &osd_display_debug_enable);
 	len = snprintf(buf, 128, "%d\n", osd_display_debug_enable);
 	return simple_read_from_buffer(userbuf, count, ppos, buf, len);
 }
@@ -187,6 +189,8 @@ static ssize_t osd_display_debug_write_file(struct file *file,
 				const char __user *userbuf,
 				size_t count, loff_t *ppos)
 {
+	struct seq_file *s = file->private_data;
+	int osd_id = *(int *)s;
 	char buf[128];
 	u32 osd_display_debug_enable;
 	int ret = 0;
@@ -196,7 +200,7 @@ static ssize_t osd_display_debug_write_file(struct file *file,
 		return -EFAULT;
 	buf[count] = 0;
 	ret = kstrtoint(buf, 0, &osd_display_debug_enable);
-	osd_set_display_debug(osd_display_debug_enable);
+	osd_set_display_debug(osd_id, osd_display_debug_enable);
 	return count;
 }

--- a/drivers/amlogic/media/osd/osd_fb.c
+++ b/drivers/amlogic/media/osd/osd_fb.c
@@ -2973,9 +2973,10 @@ static ssize_t show_osd_display_debug(struct device *device,
 				struct device_attribute *attr,
 				char *buf)
 {
+	struct fb_info *fb_info = dev_get_drvdata(device);
 	u32 osd_display_debug_enable;

-	osd_get_display_debug(&osd_display_debug_enable);
+	osd_get_display_debug(fb_info->node, &osd_display_debug_enable);
 	return snprintf(buf, 40, "%d\n",
 		osd_display_debug_enable);
 }
@@ -2984,13 +2985,14 @@ static ssize_t store_osd_display_debug(struct device *device,
 			   struct device_attribute *attr,
 			   const char *buf, size_t count)
 {
+	struct fb_info *fb_info = dev_get_drvdata(device);
 	int res = 0;
 	int ret = 0;

 	ret = kstrtoint(buf, 0, &res);
 	if (ret < 0)
 		return -EINVAL;
-	osd_set_display_debug(res);
+	osd_set_display_debug(fb_info->node, res);

 	return count;
 }
@@ -3706,6 +3708,12 @@ static struct device_attribute osd_attrs_viu2[] = {
 			show_osd_rotate, store_osd_rotate),
 	__ATTR(osd_status, 0444,
 			show_osd_status, NULL),
+	__ATTR(osd_hwc_enable, 0644,
+			show_osd_hwc_enalbe, store_osd_hwc_enalbe),
+	__ATTR(osd_hold_line, 0644,
+			show_osd_hold_line, store_osd_hold_line),
+	__ATTR(osd_do_hwc, 0220,
+			NULL, store_do_hwc),
 };

 #ifdef CONFIG_PM
--- a/drivers/amlogic/media/osd/osd_hw.c
+++ b/drivers/amlogic/media/osd/osd_hw.c
@@ -468,6 +468,24 @@ struct hw_osd_reg_s hw_osd_reg_array_tl1[HW_OSD_COUNT] = {
 		}
 };

+#define VIU2_OSD_REG_NUM    13
+static u32 viu2_osd_table[VIU2_OSD_REG_NUM];
+static struct viu2_osd_reg_item viu2_osd_reg_table[VIU2_OSD_REG_NUM] = {
+		{VIU2_OSD1_CTRL_STAT, 0, 0xc01ff9f7},
+		{VIU2_OSD1_CTRL_STAT2, 0x0, 0x00007fff},
+		{VIU2_OSD1_BLK0_CFG_W0, 0x0, 0x70ffff7f},
+		{VIU2_OSD1_BLK0_CFG_W1, 0x0, 0x1fff1fff},
+		{VIU2_OSD1_BLK0_CFG_W2, 0x0, 0x1fff1fff},
+		{VIU2_OSD1_BLK0_CFG_W3, 0x0, 0x0fff0fff},
+		{VIU2_OSD1_BLK0_CFG_W4, 0x0, 0x0fff0fff},
+		{VIU2_OSD1_BLK1_CFG_W4, 0x0, 0xffffffff},
+		{VIU2_OSD1_BLK2_CFG_W4, 0x0, 0xffffffff},
+		{VIU2_OSD1_FIFO_CTRL_STAT, 0x0, 0xffc7ffff},
+		{VIU2_OSD1_PROT_CTRL, 0x0, 0xffff0000},
+		{VIU2_OSD1_MALI_UNPACK_CTRL, 0x0, 0x9f01ffff},
+		{VIU2_OSD1_DIMM_CTRL, 0x0, 0x7fffffff},
+};
+
 static int osd_setting_blending_scope(u32 index);
 static int vpp_blend_setting_default(u32 index);

@@ -608,14 +626,11 @@ module_param(enable_vd_zorder, uint, 0664);

 static int vsync_enter_line_max;
 static int vsync_exit_line_max;
-static int vsync_line_threshold = 950;
 static int line_threshold = 90;
 MODULE_PARM_DESC(vsync_enter_line_max, "\n vsync_enter_line_max\n");
 module_param(vsync_enter_line_max, uint, 0664);
 MODULE_PARM_DESC(vsync_exit_line_max, "\n vsync_exit_line_max\n");
 module_param(vsync_exit_line_max, uint, 0664);
-MODULE_PARM_DESC(vsync_line_threshold, "\n vsync_line_threshold\n");
-module_param(vsync_line_threshold, uint, 0664);
 MODULE_PARM_DESC(line_threshold, "\n line_threshold\n");
 module_param(line_threshold, uint, 0664);

@@ -878,13 +893,18 @@ static void f2v_get_vertical_phase(
 static bool osd_hdr_on;
 #endif

-static int get_encp_line(void)
+static int get_encp_line(u32 viu_type)
 {
 	int enc_line = 0;
 	int active_line_begin = 0;
 	unsigned int reg = 0;
+	u32 viu = VIU1;

-	switch (osd_reg_read(VPU_VIU_VENC_MUX_CTRL) & 0x3) {
+	if (viu_type == VIU1)
+		viu = osd_reg_read(VPU_VIU_VENC_MUX_CTRL) & 0x3;
+	else if (viu_type == VIU2)
+		viu = (osd_reg_read(VPU_VIU_VENC_MUX_CTRL) >> 2) & 0x3;
+	switch (viu) {
 	case 0:
 		reg = osd_reg_read(ENCL_INFO_READ);
 		active_line_begin =
@@ -911,21 +931,21 @@ static int get_encp_line(void)
 	return enc_line;
 }

-static int get_enter_encp_line(void)
+static int get_enter_encp_line(u32 viu_type)
 {
 	int enc_line = 0;

-	enc_line = get_encp_line();
+	enc_line = get_encp_line(viu_type);
 	if (enc_line > vsync_enter_line_max)
 		vsync_enter_line_max = enc_line;
 	return enc_line;
 }

-static int get_exit_encp_line(void)
+static int get_exit_encp_line(u32 viu_type)
 {
 	int enc_line = 0;

-	enc_line = get_encp_line();
+	enc_line = get_encp_line(viu_type);
 	if (enc_line > vsync_exit_line_max)
 		vsync_exit_line_max = enc_line;
 	return enc_line;
@@ -1373,7 +1393,7 @@ int osd_sync_request_render(u32 index, u32 yres,
 	int line, hwc_enable;
 	u32 output_index = 0;

-	line = get_encp_line();
+	line = get_encp_line(output_index);
 	output_index = get_output_device_id(index);
 	osd_log_dbg2(MODULE_RENDER,
 			"enter osd_sync_request_render:encp line=%d\n",
@@ -1400,7 +1420,7 @@ int osd_sync_do_hwc(u32 index, struct do_hwc_cmd_s *hwc_cmd)
 	u32 output_index = 0;

 	output_index = get_output_device_id(index);
-	line = get_encp_line();
+	line = get_encp_line(output_index);
 	osd_log_dbg2(MODULE_RENDER,
 		"enter osd_sync_do_hwc:encp line=%d\n",
 		line);
@@ -2132,6 +2152,125 @@ static int notify_to_amvideo(void)
 	return 0;
 }
 /*************** end of GXL/GXM hardware alpha bug workaround ***************/
+static void viu2_osd_reg_table_init(void)
+{
+	int i = 0;
+
+	for (i = 0; i < VIU2_OSD_REG_NUM; i++) {
+		viu2_osd_reg_table[i].val =
+			osd_reg_read(viu2_osd_reg_table[i].addr)
+			& viu2_osd_reg_table[i].mask;
+		viu2_osd_table[i] = viu2_osd_reg_table[i].val;
+		osd_log_dbg(MODULE_VIU2, "init: reg:%x = %x\n",
+			viu2_osd_reg_table[i].addr,
+			viu2_osd_reg_table[i].val);
+	}
+}
+
+static void viu2_osd_reg_table_write(u32 index)
+{
+
+	if ((viu2_osd_table[index] & viu2_osd_reg_table[index].mask) !=
+		(viu2_osd_reg_table[index].val &
+		viu2_osd_reg_table[index].mask)) {
+		/* not same, need write to hw regs*/
+		osd_reg_write(viu2_osd_reg_table[index].addr,
+			viu2_osd_table[index] & viu2_osd_reg_table[index].mask);
+		viu2_osd_reg_table[index].val =
+			viu2_osd_table[index] & viu2_osd_reg_table[index].mask;
+		osd_log_dbg(MODULE_VIU2, "write: reg:%x = %x, update table:%x\n",
+			viu2_osd_reg_table[index].addr,
+			viu2_osd_table[index],
+			viu2_osd_reg_table[index].val);
+	}
+}
+
+u32 viu2_osd_reg_read(u32 addr)
+{
+	int i = 0;
+
+	for (i = 0; i < VIU2_OSD_REG_NUM; i++) {
+		if (addr == viu2_osd_reg_table[i].addr)
+			return viu2_osd_table[i];
+	}
+	return 0;
+}
+
+void viu2_osd_reg_set(u32 addr, u32 val)
+{
+	int i = 0;
+
+	osd_log_dbg2(MODULE_VIU2, "%s: reg:%x, val=%x\n",
+		__func__, addr, val);
+	for (i = 0; i < VIU2_OSD_REG_NUM; i++) {
+		if (addr == viu2_osd_reg_table[i].addr) {
+			viu2_osd_table[i] = val;
+			osd_log_dbg2(MODULE_VIU2, "%s: set table:%x\n",
+				__func__,
+				viu2_osd_table[i]);
+			viu2_osd_reg_table_write(i);
+			break;
+		}
+	}
+}
+
+void viu2_osd_reg_set_bits(u32 addr, u32 val, u32 start, u32 len)
+{
+	int i = 0;
+
+	osd_log_dbg2(MODULE_VIU2, "%s: reg:%x,val=%x,%x,%x\n",
+		__func__, addr, val, start, len);
+	for (i = 0; i < VIU2_OSD_REG_NUM; i++) {
+		if (addr == viu2_osd_reg_table[i].addr) {
+			viu2_osd_table[i] = ((viu2_osd_table[i] &
+					 ~(((1L << (len)) - 1) << (start))) |
+					(((val) & ((1L << (len)) - 1))
+					<< (start)));
+			osd_log_dbg2(MODULE_VIU2, "%s: set table:%x\n",
+				__func__,
+				viu2_osd_table[i]);
+			viu2_osd_reg_table_write(i);
+			break;
+		}
+	}
+}
+
+void viu2_osd_reg_set_mask(u32 addr, u32 _mask)
+{
+	int i = 0;
+
+	osd_log_dbg2(MODULE_VIU2, "%s: reg:%x, mask:%x\n",
+		__func__, addr, _mask);
+	for (i = 0; i < VIU2_OSD_REG_NUM; i++) {
+		if (addr == viu2_osd_reg_table[i].addr) {
+			viu2_osd_table[i] = (viu2_osd_table[i] | (_mask));
+			osd_log_dbg2(MODULE_VIU2, "%s: set table:%x\n",
+				__func__,
+				viu2_osd_table[i]);
+			viu2_osd_reg_table_write(i);
+			break;
+		}
+	}
+}
+
+void viu2_osd_reg_clr_mask(u32 addr, u32 _mask)
+{
+	int i = 0;
+
+	osd_log_dbg2(MODULE_VIU2, "%s: reg:%x, mask:%x\n",
+		__func__, addr, _mask);
+	for (i = 0; i < VIU2_OSD_REG_NUM; i++) {
+		if (addr == viu2_osd_reg_table[i].addr) {
+			viu2_osd_table[i] = (viu2_osd_table[i] & (~(_mask)));
+			osd_log_dbg2(MODULE_VIU2, "%s: set table:%x\n",
+				__func__,
+				viu2_osd_table[i]);
+			viu2_osd_reg_table_write(i);
+			break;
+		}
+	}
+}
+
 #ifdef FIQ_VSYNC
 static irqreturn_t vsync_isr(int irq, void *dev_id)
 {
@@ -2171,7 +2310,7 @@ static void osd_viu2_fiq_isr(void)
 static irqreturn_t vsync_viu2_isr(int irq, void *dev_id)
 #endif
 {
-	osd_update_scan_mode_viu2();
+	/* osd_update_scan_mode_viu2(); */
 	osd_update_vsync_hit_viu2();
 #ifndef FIQ_VSYNC
 	return IRQ_HANDLED;
@@ -2256,7 +2395,7 @@ static void osd_wait_vsync_hw_viu2(void)
 				timeout = msecs_to_jiffies(1000);
 		}
 		wait_event_interruptible_timeout(
-				osd_vsync_wq, vsync_hit[VIU2], timeout);
+				osd_vsync2_wq, vsync_hit[VIU2], timeout);
 	}
 }

@@ -3059,7 +3198,7 @@ void osd_set_window_axis_hw(u32 index, s32 x0, s32 y0, s32 x1, s32 y1)
 		osd_set_dummy_data(index, 0xff);
 	osd_update_window_axis = true;
 	if (osd_hw.hwc_enable[output_index] &&
-	    (osd_hw.osd_display_debug == OSD_DISP_DEBUG))
+	    (osd_hw.osd_display_debug[output_index] == OSD_DISP_DEBUG))
 		osd_setting_blend(output_index);
 	mutex_unlock(&osd_mutex);
 }
@@ -3255,7 +3394,7 @@ void osd_enable_hw(u32 index, u32 enable)
 		add_to_update_list(index, OSD_ENABLE);
 		osd_wait_vsync_hw(index);
 	} else if (osd_hw.hwc_enable[output_index] &&
-		osd_hw.osd_display_debug)
+		osd_hw.osd_display_debug[output_index])
 		osd_setting_blend(output_index);
 }

@@ -3613,14 +3752,20 @@ void osd_set_fps(u32 index, u32 osd_fps_start)
 	}
 }

-void osd_get_display_debug(u32 *osd_display_debug_enable)
+void osd_get_display_debug(u32 index, u32 *osd_display_debug_enable)
 {
-	*osd_display_debug_enable = osd_hw.osd_display_debug;
+	u32 output_index;
+
+	output_index = get_output_device_id(index);
+	*osd_display_debug_enable = osd_hw.osd_display_debug[output_index];
 }

-void osd_set_display_debug(u32 osd_display_debug_enable)
+void osd_set_display_debug(u32 index, u32 osd_display_debug_enable)
 {
-	osd_hw.osd_display_debug = osd_display_debug_enable;
+	u32 output_index;
+
+	output_index = get_output_device_id(index);
+	osd_hw.osd_display_debug[output_index] = osd_display_debug_enable;
 }

 void osd_get_background_size(u32 index, struct display_flip_info_s *disp_info)
@@ -4427,7 +4572,7 @@ static void osd_pan_display_single_fence(struct osd_fence_map_s *fence_map)
 			if ((osd_hw.free_scale_enable[index]
 					&& osd_update_window_axis)
 					|| freescale_update) {
-				if (!osd_hw.osd_display_debug)
+				if (!osd_hw.osd_display_debug[output_index])
 				osd_hw.reg[DISP_FREESCALE_ENABLE]
 					.update_func(index);
 				osd_update_window_axis = false;
@@ -4439,7 +4584,7 @@ static void osd_pan_display_single_fence(struct osd_fence_map_s *fence_map)
 				&& (skip == false)
 				&& (suspend_flag == false)) {
 				osd_hw.enable[index] = osd_enable;
-				if (!osd_hw.osd_display_debug)
+				if (!osd_hw.osd_display_debug[output_index])
 					osd_hw.reg[OSD_ENABLE]
 					.update_func(index);
 			}
@@ -4551,7 +4696,7 @@ static void osd_pan_display_single_fence(struct osd_fence_map_s *fence_map)
 					&& osd_update_window_axis)
 					|| (osd_hw.free_scale_enable[index]
 					&& freescale_update)) {
-				if (!osd_hw.osd_display_debug)
+				if (!osd_hw.osd_display_debug[output_index])
 					osd_hw.reg[DISP_FREESCALE_ENABLE]
 						.update_func(index);
 				osd_update_window_axis = false;
@@ -4563,7 +4708,7 @@ static void osd_pan_display_single_fence(struct osd_fence_map_s *fence_map)
 				&& (skip == false)
 				&& (suspend_flag == false)) {
 				osd_hw.enable[index] = osd_enable;
-				if (!osd_hw.osd_display_debug)
+				if (!osd_hw.osd_display_debug[output_index])
 					osd_hw.reg[OSD_ENABLE]
 					.update_func(index);
 			}
@@ -4578,7 +4723,7 @@ static void osd_pan_display_single_fence(struct osd_fence_map_s *fence_map)
 			spin_lock_irqsave(&osd_lock, lock_flags);
 			if (suspend_flag == false) {
 				osd_hw.enable[index] = osd_enable;
-				if (!osd_hw.osd_display_debug)
+				if (!osd_hw.osd_display_debug[output_index])
 					osd_hw.reg[OSD_ENABLE]
 					.update_func(index);
 			}
@@ -4855,7 +5000,7 @@ static void _osd_pan_display_layers_fence(
 			save_layer_info(layer_map);
 	}
 	/* set hw regs */
-	if (osd_hw.osd_display_debug != OSD_DISP_DEBUG)
+	if (osd_hw.osd_display_debug[output_index] != OSD_DISP_DEBUG)
 		osd_setting_blend(output_index);
 out:
 	/* signal out fence */
@@ -6790,7 +6935,7 @@ static void osd_set_freescale(u32 index,
 		osd_log_err("error osd index=%d\n", index);
 		return;
 	}
-	if (!(osd_hw.osd_display_debug &&
+	if (!(osd_hw.osd_display_debug[output_index] &&
 		!osd_hw.free_scale_enable[index])) {
 		osd_hw.free_scale_enable[index] = 0x10001;
 		osd_hw.free_scale[index].h_enable = 1;
@@ -7791,7 +7936,7 @@ static void osd_set_freescale_new(u32 index,
 	}
 	output_index = get_output_device_id(index);

-	if (!(osd_hw.osd_display_debug &&
+	if (!(osd_hw.osd_display_debug[output_index] &&
 		!osd_hw.free_scale_enable[index])) {
 		osd_hw.free_scale_enable[index] = 0x10001;
 		osd_hw.free_scale[index].h_enable = 1;
@@ -8364,7 +8509,7 @@ static int osd_setting_order(u32 output_index)
 		set_blend_path_new(blending);
 	else
 		set_blend_path(blending);
-	line1 = get_enter_encp_line();
+	line1 = get_enter_encp_line(VIU1);
 	vinfo_height = osd_hw.field_out_en[output_index] ?
 		(osd_hw.vinfo_height[output_index] * 2) :
 		osd_hw.vinfo_height[output_index];
@@ -8374,7 +8519,7 @@ static int osd_setting_order(u32 output_index)
 			"enter osd_setting_order:encp line=%d\n",
 			line1);
 		osd_wait_vsync_hw_viu1();
-		line1 = get_enter_encp_line();
+		line1 = get_enter_encp_line(VIU1);
 	}
 	spin_lock_irqsave(&osd_lock, lock_flags);
 	if (blending->osd1_freescale_disable)
@@ -8447,7 +8592,7 @@ static int osd_setting_order(u32 output_index)
 	rdma_dt_cnt++;
 	VSYNCOSD_WR_MPEG_REG(RDMA_DETECT_REG, rdma_dt_cnt);
 	spin_unlock_irqrestore(&osd_lock, lock_flags);
-	line2 = get_exit_encp_line();
+	line2 = get_exit_encp_line(VIU1);
 	osd_log_dbg2(MODULE_RENDER,
 		"enter osd_setting_order:encp line=%d\n",
 		line2);
@@ -8602,7 +8747,7 @@ static bool set_old_hwc_freescale(u32 index)

 static void osd_setting_old_hwc(void)
 {
-	int index = OSD1;
+	int index = OSD1, output_index = VIU1;
 	bool freescale_update = false;
 	static u32 osd_enable;

@@ -8622,7 +8767,7 @@ static void osd_setting_old_hwc(void)
 	if ((osd_hw.free_scale_enable[index]
 		&& osd_update_window_axis)
 		|| freescale_update) {
-		if (!osd_hw.osd_display_debug) {
+		if (!osd_hw.osd_display_debug[output_index]) {
 			osd_set_scan_mode(index);
 			osd_hw.reg[OSD_FREESCALE_COEF]
 				.update_func(index);
@@ -8632,7 +8777,7 @@ static void osd_setting_old_hwc(void)
 		osd_update_window_axis = false;
 	}
 	if (osd_enable != osd_hw.enable[index]
-		&& (!osd_hw.osd_display_debug)
+		&& (!osd_hw.osd_display_debug[output_index])
 		&& (suspend_flag == false)) {
 		osd_hw.reg[OSD_ENABLE]
 		.update_func(index);
@@ -8645,7 +8790,10 @@ static void osd_setting_old_hwc(void)
 static void osd_setting_viu2(void)
 {
 	int index = osd_hw.osd_meson_dev.viu2_index;
+	struct hw_osd_reg_s *osd_reg = &hw_osd_reg_array[index];
+	static int count;

+	count++;
 	if (!osd_hw.osd_afbcd[index].enable)
 		canvas_config(osd_hw.fb_gem[index].canvas_idx,
 			osd_hw.fb_gem[index].addr,
@@ -8654,12 +8802,37 @@ static void osd_setting_viu2(void)
 			CANVAS_ADDR_NOWRAP,
 			CANVAS_BLKMODE_LINEAR);
 	osd_hw.reg[OSD_COLOR_MODE].update_func(index);
-	/* geometry and freescale need update with ioctl */
-	osd_hw.reg[DISP_GEOMETRY].update_func(index);
-	osd_hw.reg[DISP_OSD_REVERSE].update_func(index);
-	if (!osd_hw.osd_display_debug)
-		osd_hw.reg[OSD_ENABLE]
-		.update_func(index);
+	if (count == 1) {
+		/* geometry and freescale need update with ioctl */
+		osd_hw.reg[DISP_GEOMETRY].update_func(index);
+		osd_hw.reg[DISP_OSD_REVERSE].update_func(index);
+		if (!osd_hw.osd_display_debug[VIU2])
+			osd_hw.reg[OSD_ENABLE]
+			.update_func(index);
+	}
+	if (!osd_hw.dim_layer[index]) {
+		VSYNCOSD_WR_MPEG_REG(osd_reg->osd_dimm_ctrl,
+			0x00000000);
+	} else {
+		u32 dimm_rgb = 0;
+
+		dimm_rgb =
+			((osd_hw.dim_color[index] & 0xff000000)
+			>> 24) << 22;
+		dimm_rgb |=
+			((osd_hw.dim_color[index] & 0xff0000)
+			>> 16) << 12;
+		dimm_rgb |=
+			((osd_hw.dim_color[index] & 0xff00)
+			>> 8) << 2;
+		VSYNCOSD_WR_MPEG_REG(osd_reg->osd_dimm_ctrl,
+			0x40000000 | dimm_rgb);
+		VSYNCOSD_WR_MPEG_REG_BITS(
+			osd_reg->osd_ctrl_stat2, 0x1, 14, 1);
+		VSYNCOSD_WR_MPEG_REG_BITS(
+			osd_reg->osd_ctrl_stat2,
+			osd_hw.dim_color[index] & 0xff, 6, 8);
+	}
 	osd_wait_vsync_hw_viu2();
 }

@@ -9631,6 +9804,7 @@ void osd_init_viu2(void)
 	osd_get_reverse_hw(idx, &data32);
 	if (data32)
 		osd_set_reverse_hw(idx, data32, 1);
+	viu2_osd_reg_table_init();
 	osd_hw.powered[idx] = 1;
 }

@@ -10906,7 +11080,7 @@ void osd_page_flip(struct osd_plane_map_s *plane_map)
 			if ((osd_hw.free_scale_enable[index]
 				&& osd_update_window_axis)
 				|| freescale_update) {
-				if (!osd_hw.osd_display_debug)
+				if (!osd_hw.osd_display_debug[output_index])
 					osd_hw.reg[DISP_FREESCALE_ENABLE]
 					.update_func(index);
 				osd_update_window_axis = false;
@@ -10915,7 +11089,7 @@ void osd_page_flip(struct osd_plane_map_s *plane_map)
 				&& (osd_enable != osd_hw.enable[index])
 				&& (suspend_flag == false)) {
 				osd_hw.enable[index] = osd_enable;
-				if (!osd_hw.osd_display_debug)
+				if (!osd_hw.osd_display_debug[output_index])
 					osd_hw.reg[OSD_ENABLE]
 						.update_func(index);
 			}
@@ -10938,7 +11112,7 @@ void osd_page_flip(struct osd_plane_map_s *plane_map)
 			if ((osd_enable != osd_hw.enable[index])
 				&& (suspend_flag == false)) {
 				osd_hw.enable[index] = osd_enable;
-				if (!osd_hw.osd_display_debug)
+				if (!osd_hw.osd_display_debug[output_index])
 					osd_hw.reg[OSD_ENABLE]
 						.update_func(index);
 			}
@@ -10979,7 +11153,8 @@ void osd_page_flip(struct osd_plane_map_s *plane_map)
 				if ((osd_hw.free_scale_enable[index]
 					&& osd_update_window_axis)
 					|| freescale_update) {
-					if (!osd_hw.osd_display_debug)
+					if (!osd_hw.osd_display_debug
+						[output_index])
 					osd_hw.reg[DISP_FREESCALE_ENABLE]
 					.update_func(index);
 					osd_update_window_axis = false;
@@ -10989,7 +11164,7 @@ void osd_page_flip(struct osd_plane_map_s *plane_map)
 				&& (osd_enable != osd_hw.enable[index])
 				&& (suspend_flag == false)) {
 				osd_hw.enable[index] = osd_enable;
-				if (!osd_hw.osd_display_debug)
+				if (!osd_hw.osd_display_debug[output_index])
 					osd_hw.reg[OSD_ENABLE]
 						.update_func(index);
 			}
--- a/drivers/amlogic/media/osd/osd_hw.h
+++ b/drivers/amlogic/media/osd/osd_hw.h
@@ -183,8 +183,8 @@ int get_logo_loaded(void);
 void set_logo_loaded(void);
 int set_osd_logo_freescaler(void);
 int is_interlaced(struct vinfo_s *vinfo);
-void osd_get_display_debug(u32 *osd_display_debug_enable);
-void osd_set_display_debug(u32 osd_display_debug_enable);
+void osd_get_display_debug(u32 index, u32 *osd_display_debug_enable);
+void osd_set_display_debug(u32 index, u32 osd_display_debug_enable);
 void osd_get_background_size(u32 index, struct display_flip_info_s *disp_info);
 void osd_set_background_size(u32 index, struct display_flip_info_s *disp_info);
 void osd_get_hdr_used(u32 *val);
@@ -230,4 +230,9 @@ void osd_set_blend_bypass(int index, u32 blend_bypass);
 u32 osd_get_blend_bypass(void);
 void set_viu2_format(u32 format);
 void osd_init_viu2(void);
+u32 viu2_osd_reg_read(u32 addr);
+void viu2_osd_reg_set(u32 addr, u32 val);
+void viu2_osd_reg_set_bits(u32 addr, u32 val, u32 start, u32 len);
+void viu2_osd_reg_set_mask(u32 addr, u32 _mask);
+void viu2_osd_reg_clr_mask(u32 addr, u32 _mask);
 #endif
--- a/drivers/amlogic/media/osd/osd_log.h
+++ b/drivers/amlogic/media/osd/osd_log.h
@@ -31,6 +31,7 @@
 #define MODULE_FENCE  (1 << 2)
 #define MODULE_BLEND  (1 << 3)
 #define MODULE_CURSOR (1 << 4)
+#define MODULE_VIU2   (1 << 5)

 extern unsigned int osd_log_level;
 extern unsigned int osd_log_module;
--- a/drivers/amlogic/media/osd/osd_rdma.c
+++ b/drivers/amlogic/media/osd/osd_rdma.c
@@ -401,10 +401,13 @@ static inline int wrtie_reg_internal(u32 addr, u32 val)
 	struct rdma_table_item request_item;
 	u32 rdma_en = 0;

-	if (!is_rdma_reg(addr))
-		rdma_en = 0;
-	else
-		rdma_en = rdma_enable;
+	if (!is_rdma_reg(addr)) {
+		/* need write at vsync, update table here */
+		viu2_osd_reg_set(addr, val);
+		return 0;
+
+	}
+	rdma_en = rdma_enable;

 	if (!rdma_en) {
 		osd_reg_write(addr, val);
@@ -452,10 +455,12 @@ u32 VSYNCOSD_RD_MPEG_REG(u32 addr)
 	unsigned long flags;
 	u32 rdma_en = 0;

-	if (!is_rdma_reg(addr))
-		rdma_en = 0;
-	else
-		rdma_en = rdma_enable;
+	if (!is_rdma_reg(addr)) {
+		/* need write at vsync, update table here */
+		val = viu2_osd_reg_read(addr);
+		return val;
+	}
+	rdma_en = rdma_enable;

 	if (rdma_en) {
 		spin_lock_irqsave(&rdma_lock, flags);
@@ -486,10 +491,12 @@ int VSYNCOSD_WR_MPEG_REG(u32 addr, u32 val)
 	int ret = 0, k = 0;
 	u32 rdma_en = 0, trace_num = 0;

-	if (!is_rdma_reg(addr))
-		rdma_en = 0;
-	else
-		rdma_en = rdma_enable;
+	if (!is_rdma_reg(addr)) {
+		/* need write at vsync, update table here */
+		viu2_osd_reg_set(addr, val);
+		return ret;
+	}
+	rdma_en = rdma_enable;

 	if (rdma_en)
 		ret = update_table_item(addr, val, 0);
@@ -517,10 +524,12 @@ int VSYNCOSD_WR_MPEG_REG_BITS(u32 addr, u32 val, u32 start, u32 len)
 	int ret = 0, k = 0;
 	u32 rdma_en = 0, trace_num = 0;

-	if (!is_rdma_reg(addr))
-		rdma_en = 0;
-	else
-		rdma_en = rdma_enable;
+	if (!is_rdma_reg(addr)) {
+		/* need write at vsync, update table here */
+		viu2_osd_reg_set_bits(addr, val, start, len);
+		return ret;
+	}
+	rdma_en = rdma_enable;

 	if (rdma_en) {
 		read_val = VSYNCOSD_RD_MPEG_REG(addr);
@@ -551,10 +560,12 @@ int VSYNCOSD_SET_MPEG_REG_MASK(u32 addr, u32 _mask)
 	int ret = 0, k = 0;
 	u32 rdma_en = 0, trace_num = 0;

-	if (!is_rdma_reg(addr))
-		rdma_en = 0;
-	else
-		rdma_en = rdma_enable;
+	if (!is_rdma_reg(addr)) {
+		/* need write at vsync, update table here */
+		viu2_osd_reg_set_mask(addr, _mask);
+		return ret;
+	}
+	rdma_en = rdma_enable;

 	if (rdma_en) {
 		read_val = VSYNCOSD_RD_MPEG_REG(addr);
@@ -584,10 +595,12 @@ int VSYNCOSD_CLR_MPEG_REG_MASK(u32 addr, u32 _mask)
 	int ret = 0, k = 0;
 	u32 rdma_en = 0, trace_num = 0;

-	if (!is_rdma_reg(addr))
-		rdma_en = 0;
-	else
-		rdma_en = rdma_enable;
+	if (!is_rdma_reg(addr)) {
+		/* need write at vsync, update table here */
+		viu2_osd_reg_clr_mask(addr, _mask);
+		return ret;
+	}
+	rdma_en = rdma_enable;

 	if (rdma_en) {
 		read_val = VSYNCOSD_RD_MPEG_REG(addr);
@@ -615,10 +628,12 @@ int VSYNCOSD_IRQ_WR_MPEG_REG(u32 addr, u32 val)
 	int ret = 0, k = 0;
 	u32 rdma_en = 0, trace_num = 0;

-	if (!is_rdma_reg(addr))
-		rdma_en = 0;
-	else
-		rdma_en = rdma_enable;
+	if (!is_rdma_reg(addr)) {
+		/* need write at vsync, update table here */
+		viu2_osd_reg_set(addr, val);
+		return ret;
+	}
+	rdma_en = rdma_enable;

 	if (rdma_en)
 		ret = update_table_item(addr, val, 1);