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clk: rockchip: add a COMPOSITE_HALFDIV_OFFSET clock-type

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The div offset of some clocks are different from their mux offset
and the COMPOSITE clock-type require that div and mux offset are
the same, so add a new COMPOSITE_DIV_OFFSET clock-type to handle
that.

Change-Id: I1c97f7464c3c80ea6dbd7d4052565dd4e35c0931
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2019-11-18 14:53:55 +08:00
committed by Tao Huang
parent 1470eea92e
commit 6795fd4467
3 changed files with 39 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/clk/rockchip/clk-half-divider.c
View File

@@ -152,10 +152,10 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
u8 num_parents, void __iomem *base,
int muxdiv_offset, u8 mux_shift,
u8 mux_width, u8 mux_flags,
u8 div_shift, u8 div_width,
u8 div_flags, int gate_offset,
u8 gate_shift, u8 gate_flags,
unsigned long flags,
int div_offset, u8 div_shift,
u8 div_width, u8 div_flags,
int gate_offset, u8 gate_shift,
u8 gate_flags, unsigned long flags,
spinlock_t *lock)
{
struct clk *clk;
@@ -197,7 +197,10 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
goto err_div;
div->flags = div_flags;
div->reg = base + muxdiv_offset;
if (div_offset)
div->reg = base + div_offset;
else
div->reg = base + muxdiv_offset;
div->shift = div_shift;
div->width = div_width;
div->lock = lock;

9
drivers/clk/rockchip/clk.c
View File

@@ -543,10 +543,11 @@ void __init rockchip_clk_register_branches(
list->parent_names, list->num_parents,
ctx->reg_base, list->muxdiv_offset,
list->mux_shift, list->mux_width,
list->mux_flags, list->div_shift,
list->div_width, list->div_flags,
list->gate_offset, list->gate_shift,
list->gate_flags, flags, &ctx->lock);
list->mux_flags, list->div_offset,
list->div_shift, list->div_width,
list->div_flags, list->gate_offset,
list->gate_shift, list->gate_flags,
flags, &ctx->lock);
break;
case branch_gate:
flags |= CLK_SET_RATE_PARENT;

30
drivers/clk/rockchip/clk.h
View File

@@ -890,6 +890,28 @@ struct rockchip_clk_branch {
.gate_flags = gf, \
}
#define COMPOSITE_HALFDIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, mf, do,\
ds, dw, df, go, gs, gf) \
{ \
.id = _id, \
.branch_type = branch_half_divider, \
.name = cname, \
.parent_names = pnames, \
.num_parents = ARRAY_SIZE(pnames), \
.flags = f, \
.muxdiv_offset = mo, \
.mux_shift = ms, \
.mux_width = mw, \
.mux_flags = mf, \
.div_offset = do, \
.div_shift = ds, \
.div_width = dw, \
.div_flags = df, \
.gate_offset = go, \
.gate_shift = gs, \
.gate_flags = gf, \
}
#define COMPOSITE_NOGATE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, \
ds, dw, df) \
{ \
@@ -974,10 +996,10 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
u8 num_parents, void __iomem *base,
int muxdiv_offset, u8 mux_shift,
u8 mux_width, u8 mux_flags,
u8 div_shift, u8 div_width,
u8 div_flags, int gate_offset,
u8 gate_shift, u8 gate_flags,
unsigned long flags,
int div_offset, u8 div_shift,
u8 div_width, u8 div_flags,
int gate_offset, u8 gate_shift,
u8 gate_flags, unsigned long flags,
spinlock_t *lock);
#ifdef CONFIG_RESET_CONTROLLER