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ANDROID: KVM: arm64: Fix initializing traps for protected VMs

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The values of the trapping registers for protected VMs should be
computed from the ground up, and not depend on potentially
preexisting values.

No functional change intended.

Signed-off-by: Fuad Tabba <tabba@google.com>
Bug: 209580772
Change-Id: Iacd3916dd1bbfc8d9cc859f94a9d879e9d456ebc
Signed-off-by: Will Deacon <willdeacon@google.com>
This commit is contained in:
Fuad Tabba
2021-11-11 13:25:10 +00:00
committed by Will Deacon
parent 504bd4048c
commit 6847b104ec
1 changed files with 16 additions and 8 deletions
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24
arch/arm64/kvm/hyp/nvhe/pkvm.c
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@@ -154,21 +154,29 @@ static void pvm_init_traps_aa64mmfr1(struct kvm_vcpu *vcpu)
*/
static void pvm_init_trap_regs(struct kvm_vcpu *vcpu)
{
const u64 hcr_trap_feat_regs = HCR_TID3;
const u64 hcr_trap_impdef = HCR_TACR | HCR_TIDCP | HCR_TID1;
vcpu->arch.cptr_el2 = CPTR_EL2_DEFAULT;
vcpu->arch.mdcr_el2 = 0;
/*
* Always trap:
* - Feature id registers: to control features exposed to guests
* - Implementation-defined features
*/
vcpu->arch.hcr_el2 |= hcr_trap_feat_regs | hcr_trap_impdef;
vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS |
HCR_TID3 | HCR_TACR | HCR_TIDCP | HCR_TID1;
/* Clear res0 and set res1 bits to trap potential new features. */
vcpu->arch.hcr_el2 &= ~(HCR_RES0);
vcpu->arch.mdcr_el2 &= ~(MDCR_EL2_RES0);
vcpu->arch.cptr_el2 |= CPTR_NVHE_EL2_RES1;
vcpu->arch.cptr_el2 &= ~(CPTR_NVHE_EL2_RES0);
if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN)) {
/* route synchronous external abort exceptions to EL2 */
vcpu->arch.hcr_el2 |= HCR_TEA;
/* trap error record accesses */
vcpu->arch.hcr_el2 |= HCR_TERR;
}
if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
vcpu->arch.hcr_el2 |= HCR_FWB;
if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE))
vcpu->arch.hcr_el2 |= HCR_TID2;
}
/*