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dtv_demod: TM2:DTV search channel [1/1]

Browse Source 
PD#SWPL-6912

Problem:
tm2 bringup

Solution:
verify basic function

Verify:
verified by tm2_t962e2_ab311

Change-Id: Icdd38ca191923be130003b82c6434b106caa8194
Signed-off-by: zhiwei.yuan <zhiwei.yuan@amlogic.com>
This commit is contained in:
zhiwei.yuan
2019-04-04 16:06:32 +08:00
committed by Jianxiong Pan
parent 2dd92a6fa9
commit 689996120f
21 changed files with 322 additions and 387 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/amlogic/tm2_pxp.dts
View File

@@ -219,7 +219,7 @@
};
aml_dtv_demod {
compatible = "amlogic, ddemod-tl1";
compatible = "amlogic, ddemod-tm2";
dev_name = "aml_dtv_demod";
status = "okay";

2
arch/arm/boot/dts/amlogic/tm2_t962e2_ab311.dts
View File

@@ -262,7 +262,7 @@
};
aml_dtv_demod {
compatible = "amlogic, ddemod-tl1";
compatible = "amlogic, ddemod-tm2";
dev_name = "aml_dtv_demod";
status = "okay";

2
arch/arm/boot/dts/amlogic/tm2_t962e2_ab319.dts
View File

@@ -258,7 +258,7 @@
};
aml_dtv_demod {
compatible = "amlogic, ddemod-tl1";
compatible = "amlogic, ddemod-tm2";
dev_name = "aml_dtv_demod";
status = "okay";

2
arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
View File

@@ -263,7 +263,7 @@
};
aml_dtv_demod {
compatible = "amlogic, ddemod-tl1";
compatible = "amlogic, ddemod-tm2";
dev_name = "aml_dtv_demod";
status = "okay";

2
arch/arm/boot/dts/amlogic/tm2_t962x3_ab309.dts
View File

@@ -259,7 +259,7 @@
};
aml_dtv_demod {
compatible = "amlogic, ddemod-tl1";
compatible = "amlogic, ddemod-tm2";
dev_name = "aml_dtv_demod";
status = "okay";

2
arch/arm64/boot/dts/amlogic/tm2_pxp.dts
View File

@@ -218,7 +218,7 @@
};
aml_dtv_demod {
compatible = "amlogic, ddemod-tl1";
compatible = "amlogic, ddemod-tm2";
dev_name = "aml_dtv_demod";
status = "okay";

2
arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311.dts
View File

@@ -258,7 +258,7 @@
};
aml_dtv_demod {
compatible = "amlogic, ddemod-tl1";
compatible = "amlogic, ddemod-tm2";
dev_name = "aml_dtv_demod";
status = "okay";

2
arch/arm64/boot/dts/amlogic/tm2_t962e2_ab319.dts
View File

@@ -258,7 +258,7 @@
};
aml_dtv_demod {
compatible = "amlogic, ddemod-tl1";
compatible = "amlogic, ddemod-tm2";
dev_name = "aml_dtv_demod";
status = "okay";

2
arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts
View File

@@ -260,7 +260,7 @@
};
aml_dtv_demod {
compatible = "amlogic, ddemod-tl1";
compatible = "amlogic, ddemod-tm2";
dev_name = "aml_dtv_demod";
status = "okay";

2
arch/arm64/boot/dts/amlogic/tm2_t962x3_ab309.dts
View File

@@ -259,7 +259,7 @@
};
aml_dtv_demod {
compatible = "amlogic, ddemod-tl1";
compatible = "amlogic, ddemod-tm2";
dev_name = "aml_dtv_demod";
status = "okay";

50
drivers/amlogic/media/dtv_demod/aml_demod.c
View File

@@ -271,9 +271,8 @@ static long aml_demod_ioctl(struct file *file,
int strength = 0;
struct dvb_frontend *dvbfe;
struct aml_tuner_sys *tuner;
//struct aml_tuner_sys tuner_para = {0};
struct aml_tuner_sys tuner_para = {0};
struct aml_demod_reg arg_t;
//static unsigned int tuner_attach_flg;
switch (cmd) {
case AML_DEMOD_GET_RSSI:
@@ -294,41 +293,30 @@ static long aml_demod_ioctl(struct file *file,
break;
case AML_DEMOD_SET_TUNER:
pr_dbg("Ioctl Demod Set Tuner.\n");
dvbfe = aml_get_fe();/*get_si2177_tuner();*/
#if 0
dvbfe = aml_get_fe();
if (dvbfe == NULL) {
PR_ERR("point fe is NULL\n");
return -EINVAL;
}
if (copy_from_user(&tuner_para, (void __user *)arg,
sizeof(struct aml_tuner_sys))) {
pr_dbg("copy error AML_DEMOD_SET_REG\n");
PR_ERR("copy error AML_DEMOD_SET_REG\n");
} else {
//pr_dbg("dvbfe = %p\n",dvbfe);
pr_dbg("tuner mode = %d\n", tuner_para.mode);
if (tuner_attach_flg == 0) {
attach_tuner_demod();
tuner_attach_flg = 1;
if (tuner_para.mode <= FE_ISDBT) {
PR_INFO("set tuner md = %d\n",
tuner_para.mode);
dvbfe->ops.info.type = tuner_para.mode;
} else {
PR_ERR("wrong md: %d\n", tuner_para.mode);
}
tuner_set_freq(tuner_para.ch_freq);
if (tuner_para.mode == FE_ATSC) {
tuner_config_atsc();
tuner_set_atsc_para();
} else if (tuner_para.mode == FE_DTMB) {
tuner_config_dtmb();
tuner_set_dtmb_para();
} else if (tuner_para.mode == FE_QAM) {
tuner_config_qam();
tuner_set_qam_para();
}
dvbfe->dtv_property_cache.frequency =
tuner_para.ch_freq;
dvbfe->ops.tuner_ops.set_config(dvbfe, NULL);
tuner_set_params(dvbfe);
}
#endif
#if 0 /*ary temp for my_tool:*/
if (dvbfe != NULL) {
pr_dbg("calling tuner ops\n");
if (dvbfe->ops.tuner_ops.set_params)
dvbfe->ops.tuner_ops.set_params(dvbfe);
}
#endif
break;
case AML_DEMOD_SET_SYS:

106
drivers/amlogic/media/dtv_demod/amlfrontend.c
View File

@@ -82,7 +82,7 @@ int aml_demod_debug = DBG_INFO;
*it's disabled as default, can be enabled if needed
*we can make it always enabled after all testing are passed
*/
static unsigned int demod_dvbc_speedup_en;
static unsigned int demod_dvbc_speedup_en = 1;
#if 0
@@ -163,6 +163,7 @@ const char *name_ic[] = {
"gxlx",
"txhd",
"tl1",
"tm2",
};
#define END_SYS_DELIVERY 19
@@ -705,7 +706,7 @@ static int amdemod_stat_islock(/*struct aml_fe_dev *dev,*/ int mode)
if ((atsc_read_iqr_reg() >> 16) == 0x1f)
ret = 1;
} else if (atsc_mode == VSB_8) {
if (is_ic_ver(IC_VER_TL1)) {
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
if (atsc_read_reg_v4(0x2e) >= 0x76)
ret = 1;
} else {
@@ -924,6 +925,11 @@ unsigned int demod_get_adc_clk(void)
return demod_status.adc_freq;
}
unsigned int demod_get_sys_clk(void)
{
return demod_status.clk_freq;
}
static int gxtv_demod_dvbc_read_status_timer
(struct dvb_frontend *fe, enum fe_status *status)
{
@@ -1114,7 +1120,7 @@ static int gxtv_demod_dvbc_set_frontend(struct dvb_frontend *fe)
param.symb_rate = c->symbol_rate / 1000;
store_dvbc_qam_mode(c->modulation, param.symb_rate);
if (!is_ic_ver(IC_VER_TL1)) {
if (!is_ic_ver(IC_VER_TL1) && !is_ic_ver(IC_VER_TM2)) {
if ((param.mode == 3) && (demod_status.tmp != Adc_mode)) {
Gxtv_Demod_Dvbc_Init(/*dev,*/ Adc_mode);
/*pr_dbg("Gxtv_Demod_Dvbc_Init,Adc_mode\n");*/
@@ -1202,7 +1208,7 @@ static int Gxtv_Demod_Dvbc_Init(/*struct aml_fe_dev *dev, */int mode)
demod_status.tmp = Cry_mode;
}
if (is_ic_ver(IC_VER_TL1)) {
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
sys.adc_clk = Adc_Clk_24M;
sys.demod_clk = Demod_Clk_167M;
demod_status.tmp = Cry_mode;
@@ -1486,7 +1492,7 @@ static int gxtv_demod_atsc_read_status
/*atsc_thread();*/
s = amdemod_atsc_stat_islock();
if (!is_ic_ver(IC_VER_TL1)) {
if (!is_ic_ver(IC_VER_TL1) && !is_ic_ver(IC_VER_TM2)) {
if ((s == 0) && (last_lock == 1)
&& (atsc_read_reg(0x0980) >= 0x76)) {
s = 1;
@@ -1511,7 +1517,7 @@ static int gxtv_demod_atsc_read_status
FE_HAS_VITERBI | FE_HAS_SYNC;
} else {
ilock = 0;
if (is_ic_ver(IC_VER_TL1)) {
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
if (timer_not_enough(D_TIMER_DETECT)) {
*status = 0;
PR_DBG("s=0\n");
@@ -1678,7 +1684,7 @@ static int gxtv_demod_atsc_set_frontend(struct dvb_frontend *fe)
else
param_j83b.symb_rate = 5361;
if (is_ic_ver(IC_VER_TL1)) {
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
//for timeshift mosaic
demod_status.clk_freq = Demod_Clk_167M;
nco_rate = (demod_status.adc_freq * 256)
@@ -1691,14 +1697,14 @@ static int gxtv_demod_atsc_set_frontend(struct dvb_frontend *fe)
dvbc_set_ch(&demod_status, /*&demod_i2c, */&param_j83b);
if (is_ic_ver(IC_VER_TL1)) {
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
qam_write_reg(0x7, 0x10f33);
set_j83b_filter_reg_v4();
qam_write_reg(0x12, 0x50e1000);
qam_write_reg(0x30, 0x41f2f69);
}
} else if (c->modulation > QAM_AUTO) {
if (is_ic_ver(IC_VER_TL1)) {
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
Val_0x6a.bits = atsc_read_reg_v4(ATSC_DEMOD_REG_0X6A);
Val_0x6a.b.peak_thd = 0x6;//Let CCFO Quality over 6
atsc_write_reg_v4(ATSC_DEMOD_REG_0X6A, Val_0x6a.bits);
@@ -1860,12 +1866,12 @@ void atsc_detect_first(struct dvb_frontend *fe, enum fe_status *status)
check_ok = 0;
for (cnt = 0; cnt < CNT_FIRST_ATSC; cnt++) {
if (!is_ic_ver(IC_VER_TL1))
if (!is_ic_ver(IC_VER_TL1) && !is_ic_ver(IC_VER_TM2))
gxtv_demod_atsc_read_ucblocks(fe, &ucblocks);
gxtv_demod_atsc_read_status(fe, &s);
if (is_ic_ver(IC_VER_TL1)) {
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
*status = s;
break;
}
@@ -2058,7 +2064,7 @@ static int gxtv_demod_atsc_tune(struct dvb_frontend *fe, bool re_tune,
/*PR_ATSC("delivery_system=%d\n", aml_demod_delivery_sys);*/
gxtv_demod_atsc_set_frontend(fe);
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
timer_begain(D_TIMER_DETECT);
if (c->modulation == QPSK) {
@@ -2078,7 +2084,7 @@ static int gxtv_demod_atsc_tune(struct dvb_frontend *fe, bool re_tune,
return 0;
}
#endif
if (is_ic_ver(IC_VER_TL1)) {
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
if (c->modulation > QAM_AUTO)
atsc_detect_first(fe, status);
else if (c->modulation <= QAM_AUTO &&
@@ -2156,7 +2162,7 @@ int Gxtv_Demod_Atsc_Init(void/*struct aml_fe_dev *dev*/)
/* 0 -DVBC, 1-DVBT, ISDBT, 2-ATSC*/
demod_status.dvb_mode = Gxtv_Atsc;
sys.adc_clk = Adc_Clk_24M; /*Adc_Clk_26M;*/
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
sys.demod_clk = Demod_Clk_250M;
else
sys.demod_clk = Demod_Clk_225M;
@@ -2442,7 +2448,7 @@ static int gxtv_demod_dtmb_read_status_old
if (is_dtmb_ver(IC_DTMB_V2)) {
s = dtmb_check_status_gxtv(fe);
} else if (is_dtmb_ver(IC_DTMB_V3)) {
if (!is_ic_ver(IC_VER_TL1))
if (!is_ic_ver(IC_VER_TL1) && !is_ic_ver(IC_VER_TM2))
s = dtmb_check_status_txl(fe);
} else {
@@ -2566,7 +2572,7 @@ int Gxtv_Demod_Dtmb_Init(struct amldtvdemod_device_s *dev)
if (is_ic_ver(IC_VER_TXL)) {
sys.adc_clk = Adc_Clk_25M;
sys.demod_clk = Demod_Clk_225M;
} else if (is_ic_ver(IC_VER_TL1)) {
} else if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
sys.adc_clk = Adc_Clk_24M;
sys.demod_clk = Demod_Clk_250M;
} else {
@@ -2754,7 +2760,7 @@ static int gxtv_demod_dvbc_tune(struct dvb_frontend *fe, bool re_tune,
timer_begain(D_TIMER_DETECT);
gxtv_demod_dvbc_read_status_timer(fe, status);
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
demod_dvbc_speed_up(status);
PR_DBG("tune finish!\n");
@@ -2999,7 +3005,7 @@ static bool enter_mode(enum aml_fe_n_mode_t mode)
dtmb_set_mem_st(memstart_dtmb);
//?, already set in Gxtv_Demod_Dtmb_Init()
if (!is_ic_ver(IC_VER_TL1))
if (!is_ic_ver(IC_VER_TL1) && !is_ic_ver(IC_VER_TM2))
demod_write_reg(DEMOD_TOP_REGC, 0x8);
} else if (mode == AM_FE_QAM_N) {
Gxtv_Demod_Dvbc_Init(/*dev,*/ Adc_mode);
@@ -3011,7 +3017,7 @@ static bool enter_mode(enum aml_fe_n_mode_t mode)
} else if (mode == AM_FE_ATSC_N) {
Gxtv_Demod_Atsc_Init();
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
timer_set_max(D_TIMER_DETECT, 4000);
} else if (mode == AM_FE_OFDM_N || mode == AM_FE_ISDBT_N) {
Gxtv_Demod_Dvbt_Init();
@@ -3172,8 +3178,20 @@ const struct meson_ddemod_data data_tl1 = {
.reserved = 0,
.offset = IC_OFFS_V4,
.ic = IC_VER_TL1,
},
}
};
const struct meson_ddemod_data data_tm2 = {
.name = "ddmode_tm2",
.icver = {
.atsc = IC_ATSC_V2,
.dvbt = IC_MD_NONE,
.dtmb = IC_DTMB_V3,
.dvbc = IC_DVBC_V3,
.reserved = 0,
.offset = IC_OFFS_V4,
.ic = IC_VER_TM2,
}
};
static const struct of_device_id meson_ddemod_match[] = {
@@ -3195,6 +3213,9 @@ static const struct of_device_id meson_ddemod_match[] = {
}, {
.compatible = "amlogic, ddemod-tl1",
.data = &data_tl1,
}, {
.compatible = "amlogic, ddemod-tm2",
.data = &data_tm2,
},
{},
};
@@ -4824,6 +4845,47 @@ static struct dvb_frontend_ops aml_dtvdm_tl1_ops = {
};
static struct dvb_frontend_ops aml_dtvdm_tm2_ops = {
#ifdef CONFIG_AMLOGIC_DVB_COMPAT
.delsys = {SYS_DVBC_ANNEX_A, SYS_DVBC_ANNEX_B, SYS_ATSC, SYS_DTMB,
SYS_ANALOG},
#else
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B, SYS_DVBC_ANNEX_A, SYS_DVBT},
#endif
.info = {
/*in aml_fe, it is 'amlogic dvb frontend' */
.name = "amlogic dtv demod tm2",
.frequency_min = 51000000,
.frequency_max = 900000000,
.frequency_stepsize = 0,
.frequency_tolerance = 0, /**/
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO |
FE_CAN_RECOVER | FE_CAN_MUTE_TS
},
.init = aml_dtvdm_init,
.sleep = aml_dtvdm_sleep,
.set_frontend = aml_dtvdm_set_parameters,
.get_frontend = aml_dtvdm_get_frontend,
.get_tune_settings = aml_dtvdm_get_tune_settings,
.read_status = aml_dtvdm_read_status,
.read_ber = aml_dtvdm_read_ber,
.read_signal_strength = aml_dtvdm_read_signal_strength,
.read_snr = aml_dtvdm_read_snr,
.read_ucblocks = aml_dtvdm_read_ucblocks,
.release = aml_dtvdm_release,
.set_property = aml_dtvdm_set_property,
.get_property = aml_dtvdm_get_property,
/*-------------*/
.tune = aml_dtvdm_tune,
.get_frontend_algo = gxtv_demod_txlx_get_frontend_algo,
};
struct dvb_frontend *aml_dtvdm_attach(const struct amlfe_exp_config *config)
{
int ic_version = get_ic_ver();
@@ -4861,6 +4923,10 @@ struct dvb_frontend *aml_dtvdm_attach(const struct amlfe_exp_config *config)
memcpy(&fe->ops, &aml_dtvdm_tl1_ops,
sizeof(struct dvb_frontend_ops));
break;
case IC_VER_TM2:
memcpy(&fe->ops, &aml_dtvdm_tm2_ops,
sizeof(struct dvb_frontend_ops));
break;
default:
PR_ERR("attach fail! ic=%d\n", ic_version);
/*return NULL;*/

163
drivers/amlogic/media/dtv_demod/demod_dbg.c
View File

@@ -40,7 +40,7 @@ static void demod_dump_atsc_reg(struct seq_file *seq)
}
}
static int seq_file_demod_dump_reg_show(struct seq_file *seq, void *v)
static int demod_dump_reg_show(struct seq_file *seq, void *v)
{
if (demod_get_current_mode() == AML_ATSC)
demod_dump_atsc_reg(seq);
@@ -64,28 +64,24 @@ static const struct file_operations __name ## _fops = { \
.release = single_release, \
}
DEFINE_SHOW_DEMOD(seq_file_demod_dump_reg);
/*cat /sys/kernel/debug/demod/dump_reg*/
DEFINE_SHOW_DEMOD(demod_dump_reg);
static struct demod_debugfs_files_t demod_debugfs_files[] = {
{"dump_reg", S_IFREG | 0644, &seq_file_demod_dump_reg_fops},
};
static int demod_dbg_dvbc_fast_search_open(struct inode *inode,
struct file *file)
static int dvbc_fast_search_open(struct inode *inode, struct file *file)
{
PR_INFO("Demod debug Open\n");
PR_DVBC("dvbc fast channel search Open\n");
return 0;
}
static int demod_dbg_dvbc_fast_search_release(struct inode *inode,
static int dvbc_fast_search_release(struct inode *inode,
struct file *file)
{
PR_INFO("Demod debug Release\n");
PR_DVBC("dvbc fast channel search Release\n");
return 0;
}
#define BUFFER_SIZE 100
static ssize_t demod_dbg_dvbc_fast_search_show(struct file *file,
static ssize_t dvbc_fast_search_show(struct file *file,
char __user *userbuf, size_t count, loff_t *ppos)
{
char buf[BUFFER_SIZE];
@@ -93,12 +89,12 @@ static ssize_t demod_dbg_dvbc_fast_search_show(struct file *file,
len = snprintf(buf, BUFFER_SIZE, "channel fast search en : %d\n",
demod_dvbc_get_fast_search());
//len += snprintf(buf + len, BUFFER_SIZE - len, "");
/*len += snprintf(buf + len, BUFFER_SIZE - len, "");*/
return simple_read_from_buffer(userbuf, count, ppos, buf, len);
}
static ssize_t demod_dbg_dvbc_fast_search_store(struct file *file,
static ssize_t dvbc_fast_search_store(struct file *file,
const char __user *userbuf, size_t count, loff_t *ppos)
{
char buf[80];
@@ -128,13 +124,123 @@ static ssize_t demod_dbg_dvbc_fast_search_store(struct file *file,
return count;
}
static const struct file_operations demod_dbg_dvbc_fast_search_fops = {
.owner = THIS_MODULE,
.open = demod_dbg_dvbc_fast_search_open,
.release = demod_dbg_dvbc_fast_search_release,
//.unlocked_ioctl = aml_demod_ioctl,
.read = demod_dbg_dvbc_fast_search_show,
.write = demod_dbg_dvbc_fast_search_store,
static int adc_clk_open(struct inode *inode, struct file *file)
{
PR_INFO("adc clk Open\n");
return 0;
}
static int adc_clk_release(struct inode *inode,
struct file *file)
{
PR_INFO("adc clk Release\n");
return 0;
}
#define BUFFER_SIZE 100
static unsigned int adc_clk;
static ssize_t adc_clk_show(struct file *file,
char __user *userbuf, size_t count, loff_t *ppos)
{
char buf[BUFFER_SIZE];
unsigned int len;
len = snprintf(buf, BUFFER_SIZE, "adc clk sys setting %dM, dbg %dM\n",
demod_get_adc_clk() / 1000, adc_clk);
/*len += snprintf(buf + len, BUFFER_SIZE - len, "");*/
return simple_read_from_buffer(userbuf, count, ppos, buf, len);
}
static void adc_clk_set(unsigned int clk)
{
int nco_rate = 0;
if (is_ic_ver(IC_VER_TL1)) {
if (clk == 24) {
dd_tvafe_hiu_reg_write(ADC_PLL_CNTL0_TL1, 0x012004e0);
dd_tvafe_hiu_reg_write(ADC_PLL_CNTL0_TL1, 0x312004e0);
dd_tvafe_hiu_reg_write(ADC_PLL_CNTL1_TL1, 0x05400000);
dd_tvafe_hiu_reg_write(ADC_PLL_CNTL2_TL1, 0xe0800000);
dd_tvafe_hiu_reg_write(ADC_PLL_CNTL0_TL1, 0x111104e0);
dtmb_write_reg(DTMB_FRONT_DDC_BYPASS, 0x6aaaaa);
dtmb_write_reg(DTMB_FRONT_SRC_CONFIG1, 0x13196596);
dtmb_write_reg(0x5b << 2, 0x50a30a25);
nco_rate = (24000 * 256) / demod_get_sys_clk() + 2;
adc_clk = 24;
} else if (clk == 25) {
dd_tvafe_hiu_reg_write(ADC_PLL_CNTL0_TL1, 0x001104c8);
dd_tvafe_hiu_reg_write(ADC_PLL_CNTL0_TL1, 0x301104c8);
dd_tvafe_hiu_reg_write(ADC_PLL_CNTL1_TL1, 0x03000000);
dd_tvafe_hiu_reg_write(ADC_PLL_CNTL2_TL1, 0xe1800000);
dd_tvafe_hiu_reg_write(ADC_PLL_CNTL0_TL1, 0x101104c8);
dtmb_write_reg(DTMB_FRONT_DDC_BYPASS, 0x62c1a5);
dtmb_write_reg(DTMB_FRONT_SRC_CONFIG1, 0x131a747d);
dtmb_write_reg(0x5b << 2, 0x4d6a0a25);
nco_rate = (25000 * 256) / demod_get_sys_clk() + 2;
adc_clk = 25;
} else {
PR_ERR("wrong setting : adc clk\n");
}
if (nco_rate != 0)
front_write_reg_v4(0x20,
((front_read_reg_v4(0x20) & ~0xff)
| (nco_rate & 0xff)));
} else {
PR_ERR("only TL1 has this functionality\n");
}
}
static ssize_t adc_clk_store(struct file *file,
const char __user *userbuf, size_t count, loff_t *ppos)
{
char buf[80];
char cmd[80], para[80];
int ret;
count = min_t(size_t, count, (sizeof(buf)-1));
if (copy_from_user(buf, userbuf, count))
return -EFAULT;
buf[count] = 0;
ret = sscanf(buf, "%s %s", cmd, para);
if (!strcmp(cmd, "adc_clk")) {
PR_INFO("set adc clk = ");
if (!strcmp(para, "24")) {
PR_INFO("24M\n");
adc_clk_set(24);
} else if (!strcmp(para, "25")) {
PR_INFO("25M\n");
adc_clk_set(25);
}
}
return count;
}
#define DEFINE_SHOW_STORE_DEMOD(__name) \
static const struct file_operations __name ## _fops = { \
.owner = THIS_MODULE, \
.open = __name ## _open, \
.release = __name ## _release, \
.read = __name ## _show, \
.write = __name ## _store, \
}
/*echo fast_search on > /sys/kernel/debug/demod/dvbc_channel_fast*/
DEFINE_SHOW_STORE_DEMOD(dvbc_fast_search);
/*echo adc_clk 24 > /sys/kernel/debug/demod/adc_clk*/
DEFINE_SHOW_STORE_DEMOD(adc_clk);
static struct demod_debugfs_files_t demod_debug_files[] = {
{"dump_reg", S_IFREG | 0644, &demod_dump_reg_fops},
{"dvbc_channel_fast", S_IFREG | 0644, &dvbc_fast_search_fops},
{"adc_clk", S_IFREG | 0644, &adc_clk_fops},
};
void aml_demod_dbg_init(void)
@@ -151,21 +257,14 @@ void aml_demod_dbg_init(void)
return;
}
for (i = 0; i < ARRAY_SIZE(demod_debugfs_files); i++) {
entry = debugfs_create_file(demod_debugfs_files[i].name,
demod_debugfs_files[i].mode,
for (i = 0; i < ARRAY_SIZE(demod_debug_files); i++) {
entry = debugfs_create_file(demod_debug_files[i].name,
demod_debug_files[i].mode,
root_entry, NULL,
demod_debugfs_files[i].fops);
demod_debug_files[i].fops);
if (!entry)
PR_INFO("Can't create debugfs seq file.\n");
}
entry = debugfs_create_file("dvbc_channel_fast", S_IFREG | 0644,
root_entry, NULL,
&demod_dbg_dvbc_fast_search_fops);
if (!entry)
PR_INFO("Can't create debugfs fast search.\n");
}
void aml_demod_dbg_exit(void)

313
drivers/amlogic/media/dtv_demod/demod_func.c
View File

@@ -132,7 +132,7 @@ void adc_dpll_setup(int clk_a, int clk_b, int clk_sys, int dvb_mode)
struct dfe_adcpll_para ddemod_pll;
int sts_pll;
if (is_ic_ver(IC_VER_TL1)) {
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
if (clk_b == Adc_Clk_24M) {
dtvpll_init_flag(1);
return;
@@ -582,14 +582,14 @@ unsigned int demod_read_demod_reg(unsigned int addr)
void power_sw_hiu_reg(int on)
{
if (on == PWR_ON) {
if (is_ic_ver(IC_VER_TL1))
if ((is_ic_ver(IC_VER_TL1)) || (is_ic_ver(IC_VER_TM2)))
dd_tvafe_hiu_reg_write(HHI_DEMOD_MEM_PD_REG, 0);
else
dd_tvafe_hiu_reg_write(HHI_DEMOD_MEM_PD_REG,
(dd_tvafe_hiu_reg_read(HHI_DEMOD_MEM_PD_REG)
& (~0x2fff)));
} else {
if (is_ic_ver(IC_VER_TL1))
if ((is_ic_ver(IC_VER_TL1)) || (is_ic_ver(IC_VER_TM2)))
dd_tvafe_hiu_reg_write(HHI_DEMOD_MEM_PD_REG,
0xffffffff);
else
@@ -610,147 +610,75 @@ void power_sw_reset_reg(int en)
}
}
void demod_power_switch(int pwr_cntl)
{
int reg_data;
#if 1
/*if (is_meson_txlx_cpu() || is_meson_txhd_cpu()) {*/
if (is_ic_ver(IC_VER_TXLX) || is_ic_ver(IC_VER_TXHD)) {
unsigned int pwr_slp_bit;
unsigned int pwr_iso_bit;
if (pwr_cntl == PWR_ON) {
if (is_ic_ver(IC_VER_TM2)) {
pwr_slp_bit = 23;
pwr_iso_bit = 23;
} else {
pwr_slp_bit = 10;
pwr_iso_bit = 14;
}
if (is_ic_ver(IC_VER_GXLX)) {
PR_DBG("[PWR]: GXLX not support power switch,power mem\n");
power_sw_hiu_reg(PWR_ON);
} else if (pwr_cntl == PWR_ON) {
PR_DBG("[PWR]: Power on demod_comp %x,%x\n",
AO_RTI_GEN_PWR_SLEEP0, AO_RTI_GEN_PWR_ISO0);
/* Powerup demod_comb */
reg_data = demod_read_ao_reg(AO_RTI_GEN_PWR_SLEEP0);
demod_set_ao_reg((reg_data & (~(0x1 << 10))),
demod_set_ao_reg((reg_data & (~(0x1 << pwr_slp_bit))),
AO_RTI_GEN_PWR_SLEEP0);
/* [10] power on */
/*PR_DBG("[PWR]: Power on demod_comp %x,%x\n",*/
/* TXLX_HHI_DEMOD_MEM_PD_REG, TXLX_RESET0_LEVEL);*/
/* Power up memory */
power_sw_hiu_reg(PWR_ON);
/* reset */
power_sw_reset_reg(1); /*reset*/
/* msleep(20);*/
power_sw_reset_reg(1);
/* remove isolation */
if (is_ic_ver(IC_VER_TM2))
/* remove isolation */
demod_set_ao_reg(
(demod_read_ao_reg(AO_RTI_GEN_PWR_ISO0) &
(~(0x3 << 14))), AO_RTI_GEN_PWR_ISO0);
/* pull up reset */
power_sw_reset_reg(0); /*reset*/
/* *P_RESET0_LEVEL |= (0x1<<8); */
} else {
PR_DBG("[PWR]: Power off demod_comp\n");
/* add isolation */
demod_set_ao_reg(
(demod_read_ao_reg(AO_RTI_GEN_PWR_ISO0) |
(0x3 << 14)), AO_RTI_GEN_PWR_ISO0);
/* power down memory */
power_sw_hiu_reg(PWR_OFF);
/* power down demod_comb */
reg_data = demod_read_ao_reg(AO_RTI_GEN_PWR_SLEEP0);
demod_set_ao_reg((reg_data | (0x1 << 10)),
AO_RTI_GEN_PWR_SLEEP0);
/* [10] power on */
}
/*} else if (is_meson_gxlx_cpu()) {*/
} else if (is_ic_ver(IC_VER_GXLX)) {
PR_DBG("[PWR]: GXLX not support power switch,power mem\n");
power_sw_hiu_reg(PWR_ON);
} else if (is_ic_ver(IC_VER_TL1)) {
if (pwr_cntl == PWR_ON) {
PR_DBG("[PWR]: Power on demod_comp %x,%x\n",
AO_RTI_GEN_PWR_SLEEP0, AO_RTI_GEN_PWR_ISO0);
/* Powerup demod_comb */
reg_data = demod_read_ao_reg(AO_RTI_GEN_PWR_SLEEP0);
demod_set_ao_reg((reg_data & (~(0x1 << 10))),
AO_RTI_GEN_PWR_SLEEP0);
/* [10] power on */
/*PR_DBG("[PWR]: Power on demod_comp %x,%x\n",*/
/* TXLX_HHI_DEMOD_MEM_PD_REG, TXLX_RESET0_LEVEL);*/
/* Power up memory */
power_sw_hiu_reg(PWR_ON);
/* reset */
power_sw_reset_reg(1); /*reset*/
/* msleep(20);*/
/* remove isolation */
demod_set_ao_reg(
(demod_read_ao_reg(AO_RTI_GEN_PWR_ISO0) &
(~(0x3 << 14))), AO_RTI_GEN_PWR_ISO0);
/* pull up reset */
power_sw_reset_reg(0); /*reset*/
/* *P_RESET0_LEVEL |= (0x1<<8); */
} else {
PR_DBG("[PWR]: Power off demod_comp\n");
/* add isolation */
demod_set_ao_reg(
(demod_read_ao_reg(AO_RTI_GEN_PWR_ISO0) |
(0x3 << 14)), AO_RTI_GEN_PWR_ISO0);
/* power down memory */
power_sw_hiu_reg(PWR_OFF);
/* power down demod_comb */
reg_data = demod_read_ao_reg(AO_RTI_GEN_PWR_SLEEP0);
demod_set_ao_reg((reg_data | (0x1 << 10)),
AO_RTI_GEN_PWR_SLEEP0);
/* [10] power on */
}
/*} else if (is_meson_gxlx_cpu()) {*/
} else {
if (pwr_cntl == PWR_ON) {
PR_DBG("[PWR]: Power on demod_comp %x,%x\n",
AO_RTI_GEN_PWR_SLEEP0, AO_RTI_GEN_PWR_ISO0);
/* Powerup demod_comb */
reg_data = demod_read_ao_reg(AO_RTI_GEN_PWR_SLEEP0);
demod_set_ao_reg((reg_data & (~(0x1 << 10))),
AO_RTI_GEN_PWR_SLEEP0);
/* [10] power on */
/*PR_DBG("[PWR]: Power on demod_comp %x,%x\n",*/
/* HHI_DEMOD_MEM_PD_REG, RESET0_LEVEL);*/
/* Power up memory */
power_sw_hiu_reg(PWR_ON);
/* reset */
power_sw_reset_reg(1); /*reset*/
/* msleep(20);*/
/* remove isolation */
(~(0x1 << pwr_iso_bit))),
AO_RTI_GEN_PWR_ISO0);
else
/* remove isolation */
demod_set_ao_reg(
(demod_read_ao_reg(AO_RTI_GEN_PWR_ISO0) &
(~(0x3 << 14))), AO_RTI_GEN_PWR_ISO0);
(~(0x3 << pwr_iso_bit))),
AO_RTI_GEN_PWR_ISO0);
/* pull up reset */
power_sw_reset_reg(0); /*reset*/
/* *P_RESET0_LEVEL |= (0x1<<8); */
power_sw_reset_reg(0);
} else {
PR_DBG("[PWR]: Power off demod_comp\n");
/* add isolation */
if (is_ic_ver(IC_VER_TM2))
/* add isolation */
demod_set_ao_reg(
(demod_read_ao_reg(AO_RTI_GEN_PWR_ISO0) |
(0x3 << 14)), AO_RTI_GEN_PWR_ISO0);
(0x1 << pwr_iso_bit)), AO_RTI_GEN_PWR_ISO0);
else
/* add isolation */
demod_set_ao_reg(
(demod_read_ao_reg(AO_RTI_GEN_PWR_ISO0) |
(0x3 << pwr_iso_bit)), AO_RTI_GEN_PWR_ISO0);
/* power down memory */
power_sw_hiu_reg(PWR_OFF);
/* power down demod_comb */
reg_data = demod_read_ao_reg(AO_RTI_GEN_PWR_SLEEP0);
demod_set_ao_reg((reg_data | (0x1 << 10)),
demod_set_ao_reg((reg_data | (0x1 << pwr_slp_bit)),
AO_RTI_GEN_PWR_SLEEP0);
/* [10] power on */
}
}
#endif
}
/* // 0 -DVBC J.83B, 1-DVBT, ISDBT, 2-ATSC,3-DTMB */
/* 0 -DVBC J.83B, 1-DVBT, ISDBT, 2-ATSC,3-DTMB */
void demod_set_mode_ts(unsigned char dvb_mode)
{
union demod_cfg0 cfg0;
@@ -760,7 +688,7 @@ void demod_set_mode_ts(unsigned char dvb_mode)
if (dvb_mode == Gxtv_Dtmb) {
cfg0.b.ts_sel = 1;
cfg0.b.mode = 1;
if (is_ic_ver(IC_VER_TL1)) {
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
cfg0.b.adc_format = 0;
cfg0.b.adc_regout = 0;
}
@@ -773,7 +701,7 @@ void demod_set_mode_ts(unsigned char dvb_mode)
cfg0.b.ts_sel = 1<<2;
cfg0.b.mode = 1<<2;
cfg0.b.adc_format = 0;
if (!is_ic_ver(IC_VER_TL1)) {
if (!is_ic_ver(IC_VER_TL1) && !is_ic_ver(IC_VER_TM2)) {
cfg0.b.adc_regout = 1;
cfg0.b.adc_regadj = 2;
}
@@ -849,7 +777,6 @@ void dtmb_write_reg(int reg_addr, int reg_data)
writel(reg_data, gbase_dtmb() + reg_addr);
mutex_unlock(&mp);
/* apb_write_reg(reg_addr,reg_data); */
}
unsigned int dtmb_read_reg(unsigned int reg_addr)
@@ -869,7 +796,7 @@ unsigned int dtmb_read_reg(unsigned int reg_addr)
}
#endif
/* */
void dvbt_write_reg(unsigned int addr, unsigned int data)
{
@@ -1006,36 +933,7 @@ int demod_set_sys(struct aml_demod_sta *demod_sta,
clk_adc, clk_dem);
mutex_init(&mp);
clocks_set_sys_defaults(dvb_mode);
#if 0 /*use dtvdemod_set_agc_pinmux*/
/* open dtv adc pinmux */
if (is_meson_txlx_cpu() || is_meson_gxlx_cpu()) {
PR_DBG("[R840][txlx_gxlx]set adc pinmux\n");
} else if (is_meson_txhd_cpu()) {
gpioDV_2 = demod_read_demod_reg(0xff634400 + (0x27 << 2));
PR_DBG("[txhd_R840]set adc pinmux,gpioDV_2 %x\n", gpioDV_2);
/* bit [11:8] */
gpioDV_2 = gpioDV_2 & 0xfffff0ff;
gpioDV_2 = gpioDV_2 | (0x1 << 8);
demod_set_demod_reg(gpioDV_2, 0xff634400 + (0x27 << 2));
PR_DBG("[R840]set adc pinmux,gpioDV_2 %x\n", gpioDV_2);
} else if (is_meson_txl_cpu()) {
gpioDV_2 = demod_read_demod_reg(0xc8834400 + (0x2e << 2));
PR_DBG("[R840]set adc pinmux,gpioDV_2 %x\n", gpioDV_2);
gpioDV_2 = gpioDV_2 | (0x1 << 22);
gpioDV_2 = gpioDV_2 & ~(0x3 << 19);
gpioDV_2 = gpioDV_2 & ~(0x1 << 23);
gpioDV_2 = gpioDV_2 & ~(0x1 << 31);
demod_set_demod_reg(gpioDV_2, 0xc8834400 + (0x2e << 2));
PR_DBG("[R840]set adc pinmux,gpioDV_2 %x\n", gpioDV_2);
} else {
gpiW_2 = demod_read_demod_reg(0xc88344c4);
gpiW_2 = gpiW_2 | (0x1 << 25);
gpiW_2 = gpiW_2 & ~(0xd << 24);
demod_set_demod_reg(gpiW_2, 0xc88344c4);
PR_DBG("[R840]set adc pinmux,gpiW_2 %x\n", gpiW_2);
}
#endif
/* set adc clk */
demod_set_adc_core_clk(clk_adc, clk_dem, dvb_mode);
/* init for dtmb */
@@ -1051,7 +949,7 @@ int demod_set_sys(struct aml_demod_sta *demod_sta,
PR_DBG("[open arbit]dtmb\n");
}
#else
if (is_ic_ver(IC_VER_TL1)) {
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
demod_write_reg(DEMOD_TOP_REGC, 0x11);
front_write_reg_v4(0x20,
((front_read_reg_v4(0x20) & ~0xff)
@@ -1075,12 +973,14 @@ int demod_set_sys(struct aml_demod_sta *demod_sta,
demod_write_reg(DEMOD_TOP_REGC, 0x8);
#endif
PR_DBG("[open arbit]dvbt,txlx\n");
} else if (is_ic_ver(IC_VER_TL1) && (dvb_mode == Gxtv_Atsc)) {
} else if ((is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
&& (dvb_mode == Gxtv_Atsc)) {
demod_write_reg(DEMOD_TOP_REGC, 0x11);
front_write_reg_v4(0x20, ((front_read_reg_v4(0x20) & ~0xff)
| (nco_rate & 0xff)));
front_write_reg_v4(0x20, (front_read_reg_v4(0x20) | (1 << 8)));
} else if (is_ic_ver(IC_VER_TL1) && (dvb_mode == Gxtv_Dvbc)) {
} else if ((is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
&& (dvb_mode == Gxtv_Dvbc)) {
nco_rate = (clk_adc * 256) / clk_dem + 2;
demod_write_reg(DEMOD_TOP_REGC, 0x11);
front_write_reg_v4(0x20, ((front_read_reg_v4(0x20) & ~0xff)
@@ -1095,91 +995,6 @@ int demod_set_sys(struct aml_demod_sta *demod_sta,
return 0;
}
//#ifdef HIGH_MEM
#if 0
int memorystart = 0x29c00000;//0x35100000;//0x1ef00000;0x9300000 7ca00000
#endif
/*TL1*/
void demod_set_sys_atsc_v4(void)
{
//int nco_rate;
#if 0//move to gxtv_demod_atsc_set_frontend()
union ATSC_DEMOD_REG_0X6A_BITS Val_0x6a;
union ATSC_EQ_REG_0XA5_BITS Val_0xa5;
union ATSC_CNTR_REG_0X20_BITS Val_0x20;
union ATSC_DEMOD_REG_0X54_BITS Val_0x54;
union ATSC_DEMOD_REG_0X55_BITS Val_0x55;
union ATSC_DEMOD_REG_0X6E_BITS Val_0x6e;
#endif
//PR_INFO("%s\n", __func__);
//nco_rate = (24*256)/224+2;// 24 | 25
//hardware_reset();
//app_apb_write_reg(0xf0c, 0x10);
//demod_write_reg(DEMOD_TOP_REGC, 0x10);//apb write enable
#if 0//move to clocks_set_sys_defaults()
//demod_front_init_cmd();
//app_apb_write_reg(0xf00*4,0x44 );
demod_write_reg(DEMOD_TOP_REG0, 0x44);
//app_apb_write_reg(0xf08*4,0x201);
demod_write_reg(DEMOD_TOP_REG8, 0x201);
#endif
#if 0//move to demod_set_sys()
//app_apb_write_reg(0xf0c*4,0x11);
demod_write_reg(DEMOD_TOP_REGC, 0x11);
//app_apb_write_reg(0xe20*4,((app_apb_read_reg(0xe20*4) &~ 0xff)
//| (nco_rate & 0xff)));
front_write_reg_v4(0x20, ((front_read_reg_v4(0x20) & ~0xff)
| (nco_rate & 0xff)));
//app_apb_write_reg(0xe20*4, (app_apb_read_reg(0xe20*4) | (1 << 8)));
front_write_reg_v4(0x20, (front_read_reg_v4(0x20) | (1 << 8)));
#endif
#if 0//move to gxtv_demod_atsc_set_frontend()
//set_cr_ck_rate();
//Read Reg
Val_0x6a.bits = atsc_read_reg_v4(ATSC_DEMOD_REG_0X6A);
Val_0xa5.bits = atsc_read_reg_v4(ATSC_EQ_REG_0XA5);
//24M begin
Val_0x54.bits = atsc_read_reg_v4(ATSC_DEMOD_REG_0X54);
Val_0x55.bits = atsc_read_reg_v4(ATSC_DEMOD_REG_0X55);
Val_0x6e.bits = atsc_read_reg_v4(ATSC_DEMOD_REG_0X6E);
//24M end
//Set Reg
Val_0x6a.b.peak_thd = 0x6;//Let CCFO Quality over 6
Val_0xa5.bits = 0x8c;//increase state 2 to state 3
//24M begin
Val_0x54.bits = 0x1aaaaa;//24m 5m if
Val_0x55.bits = 0x3ae28d;//24m
Val_0x6e.bits = 0x16e3600;
//24M end
//Write Reg
atsc_write_reg_v4(ATSC_DEMOD_REG_0X6A, Val_0x6a.bits);
atsc_write_reg_v4(ATSC_EQ_REG_0XA5, Val_0xa5.bits);
//24M begin
atsc_write_reg_v4(ATSC_DEMOD_REG_0X54, Val_0x54.bits);
atsc_write_reg_v4(ATSC_DEMOD_REG_0X55, Val_0x55.bits);
atsc_write_reg_v4(ATSC_DEMOD_REG_0X6E, Val_0x6e.bits);
//24M end
//atsc_reset();
Val_0x20.bits = atsc_read_reg_v4(ATSC_CNTR_REG_0X20);
Val_0x20.b.cpu_rst = 1;
atsc_write_reg_v4(ATSC_CNTR_REG_0X20, Val_0x20.bits);
Val_0x20.b.cpu_rst = 0;
atsc_write_reg_v4(ATSC_CNTR_REG_0X20, Val_0x20.bits);
usleep_range(5000, 5001);
#endif
}
/*TL1*/
void set_j83b_filter_reg_v4(void)
{
@@ -1878,38 +1693,14 @@ unsigned int dvbc_read_reg(unsigned int addr)
return tmp;
}
void dvbc_write_reg_v4(unsigned int addr, unsigned int data)
{
mutex_lock(&mp);
/* printk("[demod][write]%x,data is %x\n",(addr),data);*/
writel(data, gbase_dvbc() + (addr << 2));
mutex_unlock(&mp);
}
unsigned int dvbc_read_reg_v4(unsigned int addr)
{
unsigned int tmp;
mutex_lock(&mp);
tmp = readl(gbase_dvbc() + (addr << 2));
mutex_unlock(&mp);
return tmp;
}
#endif
void demod_write_reg(unsigned int addr, unsigned int data)
{
mutex_lock(&mp);
/* printk("[demod][write]%x,data is %x\n",(addr),data);*/
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
writel(data, gbase_demod() + (addr << 2));
else
writel(data, gbase_demod() + addr);
@@ -1922,7 +1713,7 @@ unsigned int demod_read_reg(unsigned int addr)
mutex_lock(&mp);
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
tmp = readl(gbase_demod() + (addr << 2));
else
tmp = readl(gbase_demod() + addr);
@@ -2094,7 +1885,7 @@ unsigned int dd_tvafe_reg_read(unsigned int addr)
void demod_set_demod_default(void)
{
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
return;
#if 0

2
drivers/amlogic/media/dtv_demod/dtmb_func.c
View File

@@ -140,7 +140,7 @@ void dtmb_all_reset(void)
dtmb_write_reg(DTMB_FRONT_46_CONFIG, 0x1a000f0f);
dtmb_write_reg(DTMB_FRONT_ST_FREQ, 0xf2400000);
dtmb_clk_set(Adc_Clk_24M);
} else if (is_ic_ver(IC_VER_TL1)) {
} else if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
if (demod_get_adc_clk() == Adc_Clk_24M) {
dtmb_write_reg(DTMB_FRONT_DDC_BYPASS, 0x6aaaaa);
dtmb_write_reg(DTMB_FRONT_SRC_CONFIG1, 0x13196596);

3
drivers/amlogic/media/dtv_demod/dvbc_func.c
View File

@@ -350,7 +350,8 @@ int dvbc_set_ch(struct aml_demod_sta *demod_sta,
if (demod_sta->ch_if == 0)
demod_sta->ch_if = 5000;
demod_sta->symb_rate = symb_rate;
if ((!is_ic_ver(IC_VER_TL1)) && is_dvbc_ver(IC_DVBC_V3))
if ((!is_ic_ver(IC_VER_TL1)) && !is_ic_ver(IC_VER_TM2)
&& is_dvbc_ver(IC_DVBC_V3))
demod_sta->adc_freq = demod_dvbc->dat0;
#if 0

33
drivers/amlogic/media/dtv_demod/dvbc_v3.c
View File

@@ -188,7 +188,7 @@ void demod_dvbc_set_qam(unsigned int qam)
case 0: /*16qam*/
qam_write_reg(0x71, 0x000a2200);
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
qam_write_reg(0x72, 0xc2b0c49);
else
qam_write_reg(0x72, 0x0c2b04a9);
@@ -210,7 +210,7 @@ void demod_dvbc_set_qam(unsigned int qam)
qam_write_reg(0x7a, 0x0019a7ff);
qam_write_reg(0x7c, 0x00111222);
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
qam_write_reg(0x7d, 0x2020305);
else
qam_write_reg(0x7d, 0x05050505);
@@ -220,7 +220,7 @@ void demod_dvbc_set_qam(unsigned int qam)
qam_write_reg(0x94, 0x0c1a1a00);
break;
case 2:/*64qam*/
if (is_ic_ver(IC_VER_TL1)) {
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
qam_write_reg(0x9c, 0x2a132100);
qam_write_reg(0x57, 0x606060d);
}
@@ -234,14 +234,14 @@ void demod_dvbc_set_qam(unsigned int qam)
qam_write_reg(0x77, 0x00035068);
qam_write_reg(0x78, 0x000ab100);
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
qam_write_reg(0x7a, 0xba7ff);
else
qam_write_reg(0x7a, 0x002ba7ff);
qam_write_reg(0x7c, 0x00111222);
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
qam_write_reg(0x7d, 0x2020305);
else
qam_write_reg(0x7d, 0x05050505);
@@ -251,7 +251,7 @@ void demod_dvbc_set_qam(unsigned int qam)
qam_write_reg(0x94, 0x0c262600);
break;
case 4://256 QAM
if (is_ic_ver(IC_VER_TL1)) {
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
qam_write_reg(0x9c, 0x2a232100);
qam_write_reg(0x57, 0x606040d);
}
@@ -276,7 +276,7 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta)
clk_freq = demod_sta->clk_freq; /* kHz */
/*no use adc_freq = demod_sta->adc_freq;*/ /* kHz */
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
adc_freq = demod_sta->adc_freq;
else
adc_freq = get_adc_freq();/*24000*/;
@@ -302,7 +302,7 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta)
/* Sw disable demod */
qam_write_reg(0x7, qam_read_reg(0x7) | (1 << 0));
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
if (agc_mode == 1) {
qam_write_reg(0x25,
qam_read_reg(0x25) & ~(0x1 << 10));
@@ -360,7 +360,7 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta)
}
PR_DVBC("max_frq_off is %x,\n", max_frq_off);
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
qam_write_reg(0xc, 0x245cf450); //MODIFIED BY QIANCHENG
else
qam_write_reg(0xb, max_frq_off & 0x3fffffff);
@@ -408,7 +408,7 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta)
/* agc control */
/* dvbc_write_reg(QAM_BASE+0x094, 0x7f800d2c);// AGC_CTRL ALPS tuner */
/* dvbc_write_reg(QAM_BASE+0x094, 0x7f80292c); // Pilips Tuner */
if (!is_ic_ver(IC_VER_TL1)) {
if (!is_ic_ver(IC_VER_TL1) && !is_ic_ver(IC_VER_TM2)) {
if ((agc_mode & 1) == 0)
/* freeze if agc */
qam_write_reg(0x25,
@@ -438,7 +438,7 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta)
/* if Adjcent channel test, maybe it need change.*/
/*20121208 ad invert*/
/*rsj//qam_write_reg(0x28, 0x0603cd10);*/
if (!is_ic_ver(IC_VER_TL1))
if (!is_ic_ver(IC_VER_TL1) && !is_ic_ver(IC_VER_TM2))
qam_write_reg(0x28,
qam_read_reg(0x28) | (adc_format << 27));
/* AGC_RFGAIN_CTRL 0x0e020800 by raymond,*/
@@ -460,7 +460,8 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta)
qam_write_reg(0x34, 0x7fff << 3);
/*if (is_meson_txlx_cpu()) {*/
if (is_ic_ver(IC_VER_TXLX) || (is_ic_ver(IC_VER_TL1))) {
if (is_ic_ver(IC_VER_TXLX) || (is_ic_ver(IC_VER_TL1))
|| is_ic_ver(IC_VER_TM2)) {
/*my_tool setting j83b mode*/
qam_write_reg(0x7, 0x10f33);
@@ -501,7 +502,7 @@ void dvbc_reg_initial(struct aml_demod_sta *demod_sta)
u32 dvbc_set_auto_symtrack(void)
{
if (is_ic_ver(IC_VER_TL1))
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2))
return 0;
qam_write_reg(0xc, 0x245bf45c); /*open track */
@@ -534,8 +535,6 @@ int dvbc_status(struct aml_demod_sta *demod_sta,
/*demod_sts->dat0 = dvbc_read_reg(QAM_BASE+0x28); */
/* demod_sts->dat0 = tuner_get_ch_power(demod_i2c);*/
demod_sts->dat1 = tuner_get_ch_power(fe);
#if 1
ftmp = demod_sts->ch_sts;
PR_DVBC("[dvbc debug] ch_sts is %x\n", ftmp);
ftmp = demod_sts->ch_snr;
@@ -559,8 +558,6 @@ int dvbc_status(struct aml_demod_sta *demod_sta,
tmp = demod_sts->ch_pow;
PR_DVBC("power is %ddb\n", (tmp & 0xffff));
#endif
return 0;
}
@@ -582,7 +579,7 @@ void dvbc_init_reg_ext(void)
/*ary move from amlfrontend.c */
qam_write_reg(0x7, 0xf33);
if (is_ic_ver(IC_VER_TL1)) {
if (is_ic_ver(IC_VER_TL1) || is_ic_ver(IC_VER_TM2)) {
qam_write_reg(0x12, 0x50e1000);
qam_write_reg(0x30, 0x41f2f69);
}

3
drivers/amlogic/media/dtv_demod/include/amlfrontend.h
View File

@@ -130,8 +130,9 @@ struct ss_reg_vt {
#define IC_VER_GXLX (0x03)
#define IC_VER_TXHD (0x04)
#define IC_VER_TL1 (0x05)
#define IC_VER_TM2 (0x06)
#define IC_VER_NUB (0x06)
#define IC_VER_NUB (0x07)
/*-----------------------*/

3
drivers/amlogic/media/dtv_demod/include/demod_dbg.h
View File

@@ -14,6 +14,9 @@
* more details.
*
*/
#define ADC_PLL_CNTL0_TL1 (0xb0 << 2)
#define ADC_PLL_CNTL1_TL1 (0xb1 << 2)
#define ADC_PLL_CNTL2_TL1 (0xb2 << 2)
struct demod_debugfs_files_t {
const char *name;

5
drivers/amlogic/media/dtv_demod/include/demod_func.h
View File

@@ -581,7 +581,6 @@ void demod_get_reg(struct aml_demod_reg *demod_reg);
int demod_set_sys(struct aml_demod_sta *demod_sta,
/*struct aml_demod_i2c *demod_i2c,*/
struct aml_demod_sys *demod_sys);
extern void demod_set_sys_atsc_v4(void);
extern void set_j83b_filter_reg_v4(void);
@@ -811,8 +810,6 @@ extern unsigned int demod_read_reg_rlt(unsigned int addr);
#endif
extern void dvbc_write_reg(unsigned int addr, unsigned int data);
extern unsigned int dvbc_read_reg(unsigned int addr);
extern void dvbc_write_reg_v4(unsigned int addr, unsigned int data);
extern unsigned int dvbc_read_reg_v4(unsigned int addr);
extern void demod_write_reg(unsigned int addr, unsigned int data);
extern unsigned int demod_read_reg(unsigned int addr);
//extern void demod_init_mutex(void);
@@ -830,7 +827,7 @@ extern unsigned int reset_reg_read(unsigned int addr);
extern void clocks_set_sys_defaults(unsigned char dvb_mode);
extern void demod_set_demod_default(void);
extern unsigned int demod_get_adc_clk(void);
extern unsigned int demod_get_sys_clk(void);
extern void debug_adc_pll(void);
extern void debug_check_reg_val(unsigned int reg_mode, unsigned int reg);

8
include/uapi/linux/dvb/aml_demod.h
View File

@@ -236,13 +236,5 @@ int cap_adc_data(struct aml_cap_data *cap);
extern unsigned int get_symbol_rate(void);
extern unsigned int get_ch_freq(void);
extern unsigned int get_modu(void);
extern void tuner_set_atsc_para(void);
extern void tuner_set_dtmb_para(void);
extern void tuner_set_qam_para(void);
extern void tuner_config_atsc(void);
extern void attach_tuner_demod(void);
extern void tuner_set_freq(unsigned int freq);
extern void tuner_config_dtmb(void);
extern void tuner_config_qam(void);
#endif /* AML_DEMOD_H */