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clk: rockchip: add support for pvtm clk
add pvtm 32K internal clock setting and select enable. Change-Id: I60225d29e16c5b96f285623260bea475c78a026a Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
@@ -11,6 +11,7 @@ obj-y += clk-mmc-phase.o
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obj-y += clk-muxgrf.o
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obj-y += clk-ddr.o
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obj-y += clk-half-divider.o
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obj-y += clk-pvtm.o
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obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
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obj-$(CONFIG_CPU_PX30) += clk-px30.o
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310
drivers/clk/rockchip/clk-pvtm.c
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310
drivers/clk/rockchip/clk-pvtm.c
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@@ -0,0 +1,310 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/clk-provider.h>
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#define CLK_SEL_EXTERNAL_32K 0
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#define CLK_SEL_INTERNAL_PVTM 1
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#define wr_msk_bit(v, off, msk) ((v) << (off) | (msk << (16 + (off))))
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struct rockchip_clock_pvtm;
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struct rockchip_clock_pvtm_info {
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u32 con;
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u32 sta;
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u32 sel_con;
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u32 sel_shift;
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u32 sel_value;
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u32 sel_mask;
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u32 div_shift;
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u32 div_mask;
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u32 (*get_value)(struct rockchip_clock_pvtm *pvtm,
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unsigned int time_us);
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int (*init_freq)(struct rockchip_clock_pvtm *pvtm);
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int (*sel_enable)(struct rockchip_clock_pvtm *pvtm);
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};
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struct rockchip_clock_pvtm {
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const struct rockchip_clock_pvtm_info *info;
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struct regmap *grf;
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struct clk *pvtm_clk;
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struct clk *clk;
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unsigned long rate;
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};
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static unsigned long xin32k_pvtm_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return 32768;
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}
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static const struct clk_ops xin32k_pvtm = {
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.recalc_rate = xin32k_pvtm_recalc_rate,
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};
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static void rockchip_clock_pvtm_delay(unsigned int delay)
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{
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unsigned int ms = delay / 1000;
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unsigned int us = delay % 1000;
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if (ms > 0) {
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if (ms < 20)
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us += ms * 1000;
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else
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msleep(ms);
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}
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if (us >= 10)
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usleep_range(us, us + 100);
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else
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udelay(us);
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}
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static int rockchip_clock_sel_internal_pvtm(struct rockchip_clock_pvtm *pvtm)
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{
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int ret = 0;
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ret = regmap_write(pvtm->grf, pvtm->info->sel_con,
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wr_msk_bit(pvtm->info->sel_value,
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pvtm->info->sel_shift,
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pvtm->info->sel_mask));
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if (ret != 0)
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pr_err("%s: fail to write register\n", __func__);
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return ret;
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}
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/* get pmu pvtm value */
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static u32 rockchip_clock_pvtm_get_value(struct rockchip_clock_pvtm *pvtm,
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u32 time_us)
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{
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const struct rockchip_clock_pvtm_info *info = pvtm->info;
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u32 val = 0, sta = 0;
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u32 clk_cnt, check_cnt;
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/* 24m clk ,24cnt=1us */
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clk_cnt = time_us * 24;
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regmap_write(pvtm->grf, info->con + 0x4, clk_cnt);
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regmap_write(pvtm->grf, info->con, wr_msk_bit(3, 0, 0x3));
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rockchip_clock_pvtm_delay(time_us);
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check_cnt = 100;
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while (check_cnt--) {
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regmap_read(pvtm->grf, info->sta, &sta);
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if (sta & 0x1)
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break;
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udelay(4);
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}
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if (check_cnt) {
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regmap_read(pvtm->grf, info->sta + 0x4, &val);
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} else {
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pr_err("%s: wait pvtm_done timeout!\n", __func__);
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val = 0;
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}
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regmap_write(pvtm->grf, info->con, wr_msk_bit(0, 0, 0x3));
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return val;
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}
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static int rockchip_clock_pvtm_init_freq(struct rockchip_clock_pvtm *pvtm)
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{
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u32 pvtm_cnt = 0;
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u32 div, time_us;
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int ret = 0;
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time_us = 1000;
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pvtm_cnt = pvtm->info->get_value(pvtm, time_us);
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pr_debug("get pvtm_cnt = %d\n", pvtm_cnt);
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/* set pvtm_div to get rate */
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div = DIV_ROUND_UP(1000 * pvtm_cnt, pvtm->rate);
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if (div > pvtm->info->div_mask) {
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pr_err("pvtm_div out of bounary! set max instead\n");
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div = pvtm->info->div_mask;
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}
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pr_debug("set div %d, rate %luKHZ\n", div, pvtm->rate);
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ret = regmap_write(pvtm->grf, pvtm->info->con,
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wr_msk_bit(div, pvtm->info->div_shift,
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pvtm->info->div_mask));
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if (ret != 0)
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goto out;
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/* pmu pvtm oscilator enable */
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ret = regmap_write(pvtm->grf, pvtm->info->con,
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wr_msk_bit(1, 1, 0x1));
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if (ret != 0)
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goto out;
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ret = pvtm->info->sel_enable(pvtm);
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out:
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if (ret != 0)
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pr_err("%s: fail to write register\n", __func__);
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return ret;
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}
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static int clock_pvtm_regitstor(struct device *dev,
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struct rockchip_clock_pvtm *pvtm)
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{
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struct clk_init_data init = {};
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struct clk_hw *clk_hw;
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/* Init the xin32k_pvtm */
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pvtm->info->init_freq(pvtm);
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init.flags = CLK_IS_ROOT;
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init.parent_names = NULL;
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init.num_parents = 0;
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init.name = "xin32k_pvtm";
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init.ops = &xin32k_pvtm;
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clk_hw = devm_kzalloc(dev, sizeof(*clk_hw), GFP_KERNEL);
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if (!clk_hw)
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return -ENOMEM;
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clk_hw->init = &init;
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/* optional override of the clockname */
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of_property_read_string_index(dev->of_node, "clock-output-names",
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0, &init.name);
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pvtm->clk = devm_clk_register(dev, clk_hw);
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if (IS_ERR(pvtm->clk))
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return PTR_ERR(pvtm->clk);
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return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
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pvtm->clk);
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}
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static const struct rockchip_clock_pvtm_info rk3368_pvtm_data = {
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.con = 0x180,
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.sta = 0x190,
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.sel_con = 0x100,
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.sel_shift = 6,
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.sel_value = CLK_SEL_INTERNAL_PVTM,
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.sel_mask = 0x1,
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.div_shift = 2,
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.div_mask = 0x3f,
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.sel_enable = rockchip_clock_sel_internal_pvtm,
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.get_value = rockchip_clock_pvtm_get_value,
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.init_freq = rockchip_clock_pvtm_init_freq,
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};
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MODULE_DEVICE_TABLE(of, rockchip_clock_pvtm_match);
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static const struct of_device_id rockchip_clock_pvtm_match[] = {
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{
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.compatible = "rockchip,rk3368-pvtm-clock",
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.data = (void *)&rk3368_pvtm_data,
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},
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};
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static int rockchip_clock_pvtm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = pdev->dev.of_node;
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const struct of_device_id *match;
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struct rockchip_clock_pvtm *pvtm;
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int error;
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u32 rate;
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pvtm = devm_kzalloc(dev, sizeof(*pvtm), GFP_KERNEL);
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if (!pvtm)
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return -ENOMEM;
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match = of_match_node(rockchip_clock_pvtm_match, np);
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if (!match)
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return -ENXIO;
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pvtm->info = (const struct rockchip_clock_pvtm_info *)match->data;
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if (!pvtm->info)
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return -EINVAL;
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if (!dev->parent || !dev->parent->of_node)
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return -EINVAL;
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pvtm->grf = syscon_node_to_regmap(dev->parent->of_node);
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if (IS_ERR(pvtm->grf))
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return PTR_ERR(pvtm->grf);
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if (!of_property_read_u32(np, "pvtm-rate", &rate))
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pvtm->rate = rate;
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else
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pvtm->rate = 32768;
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pvtm->pvtm_clk = devm_clk_get(&pdev->dev, "pvtm_pmu_clk");
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if (IS_ERR(pvtm->pvtm_clk)) {
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error = PTR_ERR(pvtm->pvtm_clk);
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if (error != -EPROBE_DEFER)
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dev_err(&pdev->dev,
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"failed to get pvtm core clock: %d\n",
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error);
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goto out_probe;
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}
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error = clk_prepare_enable(pvtm->pvtm_clk);
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if (error) {
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dev_err(&pdev->dev, "failed to enable the clock: %d\n",
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error);
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goto out_probe;
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}
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platform_set_drvdata(pdev, pvtm);
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error = clock_pvtm_regitstor(&pdev->dev, pvtm);
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if (error) {
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dev_err(&pdev->dev, "failed to registor clock: %d\n",
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error);
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goto out_clk_put;
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}
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return error;
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out_clk_put:
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clk_disable_unprepare(pvtm->pvtm_clk);
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out_probe:
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return error;
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}
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static int rockchip_clock_pvtm_remove(struct platform_device *pdev)
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{
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struct rockchip_clock_pvtm *pvtm = platform_get_drvdata(pdev);
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struct device_node *np = pdev->dev.of_node;
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of_clk_del_provider(np);
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clk_disable_unprepare(pvtm->pvtm_clk);
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return 0;
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}
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static struct platform_driver rockchip_clock_pvtm_driver = {
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.driver = {
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.name = "rockchip-clcok-pvtm",
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.of_match_table = rockchip_clock_pvtm_match,
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},
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.probe = rockchip_clock_pvtm_probe,
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.remove = rockchip_clock_pvtm_remove,
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};
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module_platform_driver(rockchip_clock_pvtm_driver);
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MODULE_DESCRIPTION("Rockchip Clock Pvtm Driver");
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MODULE_LICENSE("GPL v2");
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