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vdin: horizontal floral stripe [1/1]

Browse Source 
PD#SWPL-7391

Problem:
when hdmi 4k, tv menu set game mode, some time have
floral stripe

Solution:
afbc write addr is same at read addr, will occur.

Verify:
tl1

Change-Id: Iac10768116dea0d3bc4175871b954d56b044f390
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
This commit is contained in:
Yong Qin
2019-05-14 09:43:55 +08:00
parent b6f686f201
commit 695390908e
5 changed files with 20 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h
View File

@@ -80,9 +80,9 @@ static struct vlock_regs_s vlock_pll_phase_setting[VLOCK_PHASE_REG_SIZE] = {
{0x300a, 0x00600000},
{0x300b, 0x06000000},
{0x300c, 0x00600000},
{0x3025, 0x00002000},
{0x3025, 0x00010000},
{0x3027, 0x00022002},
{0x3028, 0x00001000},
{0x3028, 0x00005000},
{0x302a, 0x00022002},
};

10
drivers/amlogic/media/enhancement/amvecm/vlock.c
View File

@@ -1231,7 +1231,8 @@ static void vlock_enable_step3_pll(void)
(org_m - 1))?(org_m - 1):(pre_m - 1);
}
m_reg_value = (tmp_value & 0xffffff00) + tar_m;
if (tar_m != (tmp_value & 0xffffff00)) {
if ((tar_m != (tmp_value & 0xffffff00)) &&
(!vlock.ss_sts)) {
vlock_set_panel_pll_m(m_reg_value);
mchang = 1;
if (vlock_debug & VLOCK_DEBUG_INFO)
@@ -1664,6 +1665,11 @@ void vlock_set_phase_en(u32 en)
pr_info("vlock phlock_en=%d\n", en);
}
u32 vlock_get_phase_en(void)
{
return vlock.phlock_en;
}
void vlock_phaselock_check(struct stvlock_sig_sts *pvlock,
struct vframe_s *vf)
{
@@ -1983,7 +1989,7 @@ void vlock_fsm_check_lock_sts(struct stvlock_sig_sts *pvlock,
if (vlock_debug & VLOCK_DEBUG_INFO)
pr_info("vlock warning: set back ss on(%d, %d)\n",
frqlock_sts, phlock_sts);
pvlock->pll_mode_pause = true;
/*pvlock->pll_mode_pause = true;*/
pvlock->ss_sts = true;
vlock_set_panel_ss(true);
}

2
drivers/amlogic/media/enhancement/amvecm/vlock.h
View File

@@ -23,7 +23,7 @@
#include <linux/amlogic/media/vfm/vframe.h>
#include "linux/amlogic/media/amvecm/ve.h"
#define VLOCK_VER "Ref.2019/4/19:disable some log"
#define VLOCK_VER "Ref.2019/5/16:finetune phase lock"
#define VLOCK_REG_NUM 33

4
drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c
View File

@@ -97,7 +97,7 @@ static bool work_mode_simple;
static int phase_lock_flag;
/*game_mode_switch_frames:min num is 5 by 1080p60hz input test*/
static int game_mode_switch_frames = 10;
static int game_mode_phlock_switch_frames = 60;
static int game_mode_phlock_switch_frames = 120;
static unsigned int dv_work_delby;
static struct vf_entry *vfe_drop_force;
@@ -1845,6 +1845,8 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
/* make sure phase lock for next few frames */
if (vlock_get_phlock_flag())
phase_lock_flag++;
else
phase_lock_flag = 0;
if (phase_lock_flag >= game_mode_phlock_switch_frames) {
if (vdin_dbg_en) {
pr_info("switch game mode (%d-->5), frame_cnt=%d\n",

7
drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h
View File

@@ -48,7 +48,7 @@
/* Ref.2019/04/25: tl1 vdin0 afbce dynamically switch support,
* vpp also should support this function
*/
#define VDIN_VER "Ref.2019/04/25"
#define VDIN_VER "Ref.2019/05/14"
/*the counter of vdin*/
#define VDIN_MAX_DEVS 2
@@ -89,9 +89,13 @@
#define VDIN_CANVAS_MAX_CNT 9
/*values of vdin game mode process flag */
/*enable*/
#define VDIN_GAME_MODE_0 (1 << 0)
/*delay 1 frame*/
#define VDIN_GAME_MODE_1 (1 << 1)
/*delay 2 frame*/
#define VDIN_GAME_MODE_2 (1 << 2)
/*when phase lock, will switch 2 to 1*/
#define VDIN_GAME_MODE_SWITCH_EN (1 << 3)
/*flag for flush vdin buff*/
@@ -448,6 +452,7 @@ extern void vdin_debugfs_init(struct vdin_dev_s *vdevp);
extern void vdin_debugfs_exit(struct vdin_dev_s *vdevp);
extern bool vlock_get_phlock_flag(void);
u32 vlock_get_phase_en(void);
extern struct vdin_dev_s *vdin_get_dev(unsigned int index);
extern void vdin_mif_config_init(struct vdin_dev_s *devp);