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ARM: dts: rockchip: rk3288: fix display related nodes

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Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I0f1dda389fe89f06495661baeb3c21edbc18dfbe
This commit is contained in:
Damon Ding
2022-11-10 19:09:31 +08:00
committed by Tao Huang
parent 1e6ad41b1d
commit 69870f9db0
1 changed files with 136 additions and 32 deletions
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168
arch/arm/boot/dts/rk3288.dtsi
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@@ -929,6 +929,65 @@
status = "disabled"; status = "disabled";
}; };
lvds: lvds {
compatible = "rockchip,rk3288-lvds";
phys = <&video_phy>;
phy-names = "phy";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
lvds_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_lvds>;
};
lvds_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_lvds>;
};
};
};
};
rgb: rgb {
compatible = "rockchip,rk3288-rgb";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcdc_rgb_pins>;
pinctrl-1 = <&lcdc_sleep_pins>;
phys = <&video_phy>;
phy-names = "phy";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
rgb_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_rgb>;
};
rgb_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_rgb>;
};
};
};
};
usbphy: usbphy { usbphy: usbphy {
compatible = "rockchip,rk3288-usb-phy"; compatible = "rockchip,rk3288-usb-phy";
#address-cells = <1>; #address-cells = <1>;
@@ -1055,8 +1114,9 @@
}; };
vopb: vop@ff930000 { vopb: vop@ff930000 {
compatible = "rockchip,rk3288-vop"; compatible = "rockchip,rk3288-vop-big";
reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
reg-names = "regs", "gamma_lut";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1080,15 +1140,25 @@
remote-endpoint = <&edp_in_vopb>; remote-endpoint = <&edp_in_vopb>;
}; };
vopb_out_mipi: endpoint@2 { vopb_out_dsi0: endpoint@2 {
reg = <2>; reg = <2>;
remote-endpoint = <&mipi_in_vopb>; remote-endpoint = <&dsi0_in_vopb>;
}; };
vopb_out_lvds: endpoint@3 { vopb_out_dsi1: endpoint@3 {
reg = <3>; reg = <3>;
remote-endpoint = <&dsi1_in_vopb>;
};
vopb_out_lvds: endpoint@4 {
reg = <4>;
remote-endpoint = <&lvds_in_vopb>; remote-endpoint = <&lvds_in_vopb>;
}; };
vopb_out_rgb: endpoint@5 {
reg = <5>;
remote-endpoint = <&rgb_in_vopb>;
};
}; };
}; };
@@ -1101,12 +1171,14 @@
clock-names = "aclk", "iface"; clock-names = "aclk", "iface";
power-domains = <&power RK3288_PD_VIO>; power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>; #iommu-cells = <0>;
rockchip,disable-device-link-resume;
status = "disabled"; status = "disabled";
}; };
vopl: vop@ff940000 { vopl: vop@ff940000 {
compatible = "rockchip,rk3288-vop"; compatible = "rockchip,rk3288-vop-lit";
reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
reg-names = "regs", "gamma_lut";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1130,15 +1202,25 @@
remote-endpoint = <&edp_in_vopl>; remote-endpoint = <&edp_in_vopl>;
}; };
vopl_out_mipi: endpoint@2 { vopl_out_dsi0: endpoint@2 {
reg = <2>; reg = <2>;
remote-endpoint = <&mipi_in_vopl>; remote-endpoint = <&dsi0_in_vopl>;
}; };
vopl_out_lvds: endpoint@3 { vopl_out_dsi1: endpoint@3 {
reg = <3>; reg = <3>;
remote-endpoint = <&dsi1_in_vopl>;
};
vopl_out_lvds: endpoint@4 {
reg = <4>;
remote-endpoint = <&lvds_in_vopl>; remote-endpoint = <&lvds_in_vopl>;
}; };
vopl_out_rgb: endpoint@5 {
reg = <5>;
remote-endpoint = <&rgb_in_vopl>;
};
}; };
}; };
@@ -1151,63 +1233,69 @@
clock-names = "aclk", "iface"; clock-names = "aclk", "iface";
power-domains = <&power RK3288_PD_VIO>; power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>; #iommu-cells = <0>;
rockchip,disable-device-link-resume;
status = "disabled"; status = "disabled";
}; };
mipi_dsi: mipi@ff960000 { dsi0: dsi@ff960000 {
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x4000>; reg = <0x0 0xff960000 0x0 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
clock-names = "ref", "pclk"; clock-names = "ref", "pclk";
resets = <&cru SRST_MIPIDSI0>;
reset-names = "apb";
power-domains = <&power RK3288_PD_VIO>; power-domains = <&power RK3288_PD_VIO>;
rockchip,grf = <&grf>; rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled"; status = "disabled";
ports { ports {
mipi_in: port { mipi_in: port {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
mipi_in_vopb: endpoint@0 { dsi0_in_vopb: endpoint@0 {
reg = <0>; reg = <0>;
remote-endpoint = <&vopb_out_mipi>; remote-endpoint = <&vopb_out_dsi0>;
}; };
mipi_in_vopl: endpoint@1 { dsi0_in_vopl: endpoint@1 {
reg = <1>; reg = <1>;
remote-endpoint = <&vopl_out_mipi>; remote-endpoint = <&vopl_out_dsi0>;
}; };
}; };
}; };
}; };
lvds: lvds@ff96c000 { dsi1: dsi@ff964000 {
compatible = "rockchip,rk3288-lvds"; compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff96c000 0x0 0x4000>; reg = <0x0 0xff964000 0x0 0x4000>;
clocks = <&cru PCLK_LVDS_PHY>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk_lvds"; clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI1>;
pinctrl-names = "lcdc"; clock-names = "ref", "pclk";
pinctrl-0 = <&lcdc_ctl>; resets = <&cru SRST_MIPIDSI1>;
reset-names = "apb";
power-domains = <&power RK3288_PD_VIO>; power-domains = <&power RK3288_PD_VIO>;
rockchip,grf = <&grf>; rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled"; status = "disabled";
ports { ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
lvds_in: port@0 { dsi1_in: port {
reg = <0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
lvds_in_vopb: endpoint@0 { dsi1_in_vopb: endpoint@0 {
reg = <0>; reg = <0>;
remote-endpoint = <&vopb_out_lvds>; remote-endpoint = <&vopb_out_dsi1>;
}; };
lvds_in_vopl: endpoint@1 { dsi1_in_vopl: endpoint@1 {
reg = <1>; reg = <1>;
remote-endpoint = <&vopl_out_lvds>; remote-endpoint = <&vopl_out_dsi1>;
}; };
}; };
}; };
@@ -1268,7 +1356,11 @@
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
clock-names = "iahb", "isfr", "cec"; clock-names = "iahb", "isfr", "cec";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hdmi_ddc>;
pinctrl-1 = <&hdmi_gpio>;
power-domains = <&power RK3288_PD_VIO>; power-domains = <&power RK3288_PD_VIO>;
unsupported-yuv-input;
status = "disabled"; status = "disabled";
ports { ports {
@@ -1666,6 +1758,11 @@
}; };
hdmi { hdmi {
hdmi_gpio: hdmi-gpio {
rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>,
<7 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdmi_cec_c0: hdmi-cec-c0 { hdmi_cec_c0: hdmi-cec-c0 {
rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
}; };
@@ -1784,11 +1881,18 @@
}; };
lcdc { lcdc {
lcdc_ctl: lcdc-ctl { lcdc_rgb_pins: lcdc-rgb-pins {
rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, rockchip,pins = <1 RK_PD3 1 &pcfg_pull_none>, /* LCDC_DCLK */
<1 RK_PD1 1 &pcfg_pull_none>, <1 RK_PD2 1 &pcfg_pull_none>, /* LCDC_DEN */
<1 RK_PD2 1 &pcfg_pull_none>, <1 RK_PD1 1 &pcfg_pull_none>, /* LCDC_VSYNC */
<1 RK_PD3 1 &pcfg_pull_none>; <1 RK_PD0 1 &pcfg_pull_none>; /* LCDC_HSYNC */
};
lcdc_sleep_pins: lcdc-sleep-pins {
rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */
<1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */
<1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */
<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_HSYNC */
}; };
}; };