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hdmirx: set rxsense sync with pddq for tl1 [1/1]

Browse Source 
PD#SWPL-5668

Problem:
recognized as dvi after suspend/resume
when connect xiaomi mtk box

Solution:
when resume, add rxsense pulse to avoid
sda pulled low by xiaomi mtk box

Verify:
TL1-T962X2_X301

Change-Id: I480cbb4376bbb0c3b38318df2e26f5cc85db3d59
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
This commit is contained in:
Hang Cheng
2019-03-12 17:25:32 +08:00
committed by Luke Go
parent 71a708c520
commit 699a75e987
3 changed files with 14 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
View File

@@ -1718,7 +1718,7 @@ static void rx_phy_resume(void)
* rxsense pulse and phy_int shottern than
* 50ms, SDA may be pulled low 800ms on MTK box
*/
rx_phy_rxsense_pulse(20, 50, 1);
rx_phy_rxsense_pulse(10, 50, 1);
}
}
hdmirx_phy_init();

2
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
View File

@@ -41,7 +41,7 @@
*
*
*/
#define RX_VER1 "ver.2019/03/14"
#define RX_VER1 "ver.2019/03/15"
/*
*
*

13
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
View File

@@ -700,8 +700,19 @@ return (unsigned int)((res.a0)&0xffffffff);
*/
void hdmirx_phy_pddq(unsigned int enable)
{
if (rx.chip_id == CHIP_ID_TL1)
uint32_t term_value =
hdmirx_rd_top(TOP_HPD_PWR5V) & 0x7;
if (rx.chip_id == CHIP_ID_TL1) {
wr_reg_hhi_bits(HHI_HDMIRX_PHY_MISC_CNTL2, _BIT(1), enable);
/* set rxsense */
if (enable)
wr_reg_hhi_bits(HHI_HDMIRX_PHY_MISC_CNTL0,
MSK(3, 0), 0);
else
wr_reg_hhi_bits(HHI_HDMIRX_PHY_MISC_CNTL0,
MSK(3, 0), term_value);
}
else
hdmirx_wr_bits_dwc(DWC_SNPS_PHYG3_CTRL,
MSK(1, 1), enable);