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ethernet: stmmac: Prepare for support more phys

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There are now two built-in phys ephy and sphy, so that use the
interface integrated_phy_power() as a public interface.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: If964436beeba1359a7ce7c764f85b50a6cf52bd7
This commit is contained in:
David Wu
2022-02-25 17:00:31 +08:00
committed by Tao Huang
parent f5f864ab51
commit 69ff4e8b15
1 changed files with 70 additions and 57 deletions
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127
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
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@@ -40,7 +40,7 @@ struct rk_gmac_ops {
void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
bool enable);
void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
void (*integrated_phy_power)(struct rk_priv_data *bsp_priv, bool up);
};
struct rk_priv_data {
@@ -217,6 +217,49 @@ static int xpcs_setup(struct rk_priv_data *bsp_priv, int mode)
((((tx) >= 0) ? soc##_GMAC_CLK_TX_DL_CFG(tx) : 0) | \
(((rx) >= 0) ? soc##_GMAC_CLK_RX_DL_CFG(rx) : 0))
/* Integrated EPHY */
#define RK_GRF_MACPHY_CON0 0xb00
#define RK_GRF_MACPHY_CON1 0xb04
#define RK_GRF_MACPHY_CON2 0xb08
#define RK_GRF_MACPHY_CON3 0xb0c
#define RK_MACPHY_ENABLE GRF_BIT(0)
#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
{
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
if (priv->phy_reset) {
/* PHY needs to be disabled before trying to reset it */
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
if (priv->phy_reset)
reset_control_assert(priv->phy_reset);
usleep_range(10, 20);
if (priv->phy_reset)
reset_control_deassert(priv->phy_reset);
usleep_range(10, 20);
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
msleep(30);
}
}
static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
{
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
if (priv->phy_reset)
reset_control_assert(priv->phy_reset);
}
#define PX30_GRF_GMAC_CON1 0x0904
/* PX30_GRF_GMAC_CON1 */
@@ -618,10 +661,16 @@ static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
}
static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
static void rk3228_integrated_phy_power(struct rk_priv_data *priv, bool up)
{
regmap_write(priv->grf, RK3228_GRF_CON_MUX,
RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
if (up) {
regmap_write(priv->grf, RK3228_GRF_CON_MUX,
RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
rk_gmac_integrated_ephy_powerup(priv);
} else {
rk_gmac_integrated_ephy_powerdown(priv);
}
}
static const struct rk_gmac_ops rk3228_ops = {
@@ -629,7 +678,7 @@ static const struct rk_gmac_ops rk3228_ops = {
.set_to_rmii = rk3228_set_to_rmii,
.set_rgmii_speed = rk3228_set_rgmii_speed,
.set_rmii_speed = rk3228_set_rmii_speed,
.integrated_phy_powerup = rk3228_integrated_phy_powerup,
.integrated_phy_power = rk3228_integrated_phy_power,
};
#define RK3288_GRF_SOC_CON1 0x0248
@@ -917,10 +966,16 @@ static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
}
static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
static void rk3328_integrated_phy_power(struct rk_priv_data *priv, bool up)
{
regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
RK3328_MACPHY_RMII_MODE);
if (up) {
regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
RK3328_MACPHY_RMII_MODE);
rk_gmac_integrated_ephy_powerup(priv);
} else {
rk_gmac_integrated_ephy_powerdown(priv);
}
}
static const struct rk_gmac_ops rk3328_ops = {
@@ -928,7 +983,7 @@ static const struct rk_gmac_ops rk3328_ops = {
.set_to_rmii = rk3328_set_to_rmii,
.set_rgmii_speed = rk3328_set_rgmii_speed,
.set_rmii_speed = rk3328_set_rmii_speed,
.integrated_phy_powerup = rk3328_integrated_phy_powerup,
.integrated_phy_power = rk3328_integrated_phy_power,
};
#define RK3366_GRF_SOC_CON6 0x0418
@@ -1707,50 +1762,6 @@ static const struct rk_gmac_ops rv1126_ops = {
.set_rmii_speed = rv1126_set_rmii_speed,
};
#define RK_GRF_MACPHY_CON0 0xb00
#define RK_GRF_MACPHY_CON1 0xb04
#define RK_GRF_MACPHY_CON2 0xb08
#define RK_GRF_MACPHY_CON3 0xb0c
#define RK_MACPHY_ENABLE GRF_BIT(0)
#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
{
if (priv->ops->integrated_phy_powerup)
priv->ops->integrated_phy_powerup(priv);
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
if (priv->phy_reset) {
/* PHY needs to be disabled before trying to reset it */
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
if (priv->phy_reset)
reset_control_assert(priv->phy_reset);
usleep_range(10, 20);
if (priv->phy_reset)
reset_control_deassert(priv->phy_reset);
usleep_range(10, 20);
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
msleep(30);
}
}
static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
{
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
if (priv->phy_reset)
reset_control_assert(priv->phy_reset);
}
static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
{
struct rk_priv_data *bsp_priv = plat->bsp_priv;
@@ -2098,8 +2109,9 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
if (bsp_priv->integrated_phy)
rk_gmac_integrated_phy_powerup(bsp_priv);
if (bsp_priv->integrated_phy && bsp_priv->ops &&
bsp_priv->ops->integrated_phy_power)
bsp_priv->ops->integrated_phy_power(bsp_priv, true);
return 0;
}
@@ -2108,8 +2120,9 @@ static void rk_gmac_powerdown(struct rk_priv_data *gmac)
{
struct device *dev = &gmac->pdev->dev;
if (gmac->integrated_phy)
rk_gmac_integrated_phy_powerdown(gmac);
if (gmac->integrated_phy && gmac->ops &&
gmac->ops->integrated_phy_power)
gmac->ops->integrated_phy_power(gmac, false);
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);