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arm64: dts: rockchip: Enable display output on rk3326 863 board

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Change-Id: I6279b56e380510fbfb5ea8858fe623fbfebaa0a8
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2018-01-09 15:17:00 +08:00
committed by Tao Huang
parent e618467937
commit 6a36cb465f
1 changed files with 88 additions and 0 deletions
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88
arch/arm64/boot/dts/rockchip/rk3326-863-lp3-v10.dts
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@@ -191,3 +191,91 @@
};
};
};
&display_subsystem {
status = "okay";
};
&dsi {
status = "okay";
panel@0 {
compatible = "aoly,sl008pa21y1285-b00", "simple-panel-dsi";
reg = <0>;
backlight = <&backlight>;
enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
prepare-delay-ms = <20>;
reset-delay-ms = <20>;
init-delay-ms = <20>;
enable-delay-ms = <120>;
disable-delay-ms = <20>;
unprepare-delay-ms = <20>;
width-mm = <108>;
height-mm = <172>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
05 78 01 11
05 14 01 29
];
panel-exit-sequence = [
05 00 01 28
05 00 01 10
];
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <65000000>;
hactive = <800>;
vactive = <1280>;
hfront-porch = <2>;
hsync-len = <18>;
hback-porch = <18>;
vfront-porch = <4>;
vsync-len = <4>;
vback-porch = <16>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
&dsi_in_vopl {
status = "disabled";
};
&mipi_dphy {
status = "okay";
};
&route_dsi {
status = "okay";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};