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PM / devfreq: rockchip_dmc: remove of_get_rk3568_timings

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For rk3568, ddr timings adjustment is no longer supported in dmc drive.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Change-Id: I63f0c5fea8c5acf8e6ef8f44b62968deb7bd823e
This commit is contained in:
YouMin Chen
2021-09-30 20:14:31 +08:00
parent afda73facd
commit 6a53296ce8
2 changed files with 5 additions and 127 deletions
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56
drivers/devfreq/rockchip_dmc.c
View File

@@ -900,42 +900,6 @@ end:
of_node_put(np_tim);
}
static void of_get_rk3568_timings(struct device *dev,
struct device_node *np, uint32_t *timing)
{
struct device_node *np_tim;
u32 *p;
struct rk3568_ddr_dts_config_timing *dts_timing;
int ret = 0;
u32 i;
dts_timing =
(struct rk3568_ddr_dts_config_timing *)(timing +
DTS_PAR_OFFSET / 4);
np_tim = of_parse_phandle(np, "ddr_timing", 0);
if (!np_tim) {
ret = -EINVAL;
goto end;
}
p = (u32 *)dts_timing;
for (i = 0; i < ARRAY_SIZE(px30_dts_timing); i++) {
ret |= of_property_read_u32(np_tim, px30_dts_timing[i],
p + i);
}
end:
if (!ret) {
dts_timing->available = 1;
} else {
dts_timing->available = 0;
dev_err(dev, "of_get_ddr_timings: fail\n");
}
of_node_put(np_tim);
}
static void of_get_rv1126_timings(struct device *dev,
struct device_node *np, uint32_t *timing)
{
@@ -1804,7 +1768,6 @@ static __maybe_unused int rk3568_dmc_init(struct platform_device *pdev,
struct rockchip_dmcfreq *dmcfreq)
{
struct arm_smccc_res res;
u32 size;
int ret;
int complt_irq;
@@ -1818,18 +1781,17 @@ static __maybe_unused int rk3568_dmc_init(struct platform_device *pdev,
/*
* first 4KB is used for interface parameters
* after 4KB * N is dts parameters
* after 4KB is dts parameters
* request share memory size 4KB * 2
*/
size = sizeof(struct rk1808_ddr_dts_config_timing);
res = sip_smc_request_share_mem(DIV_ROUND_UP(size, 4096) + 1,
SHARE_PAGE_TYPE_DDR);
res = sip_smc_request_share_mem(2, SHARE_PAGE_TYPE_DDR);
if (res.a0 != 0) {
dev_err(&pdev->dev, "no ATF memory for init\n");
return -ENOMEM;
}
ddr_psci_param = (struct share_params *)res.a1;
of_get_rk3568_timings(&pdev->dev, pdev->dev.of_node,
(uint32_t *)ddr_psci_param);
/* Clear ddr_psci_param, size is 4KB * 2 */
memset_io(ddr_psci_param, 0x0, 4096 * 2);
/* start mcu with sip_smc_dram */
wait_ctrl.dcf_en = 2;
@@ -1854,14 +1816,6 @@ static __maybe_unused int rk3568_dmc_init(struct platform_device *pdev,
}
disable_irq(complt_irq);
if (of_property_read_u32(pdev->dev.of_node, "update_drv_odt_cfg",
&ddr_psci_param->update_drv_odt_cfg))
ddr_psci_param->update_drv_odt_cfg = 0;
if (of_property_read_u32(pdev->dev.of_node, "update_deskew_cfg",
&ddr_psci_param->update_deskew_cfg))
ddr_psci_param->update_deskew_cfg = 0;
res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
ROCKCHIP_SIP_CONFIG_DRAM_INIT);
if (res.a0) {

76
drivers/devfreq/rockchip_dmc_timing.h
View File

@@ -1003,82 +1003,6 @@ struct rk3399_dram_timing {
unsigned int phy_lpddr4_odt;
};
struct rk3568_ddr_dts_config_timing {
unsigned int ddr2_speed_bin;
unsigned int ddr3_speed_bin;
unsigned int ddr4_speed_bin;
unsigned int pd_idle;
unsigned int sr_idle;
unsigned int sr_mc_gate_idle;
unsigned int srpd_lite_idle;
unsigned int standby_idle;
unsigned int auto_pd_dis_freq;
unsigned int auto_sr_dis_freq;
/* for ddr2 only */
unsigned int ddr2_dll_dis_freq;
/* for ddr3 only */
unsigned int ddr3_dll_dis_freq;
/* for ddr4 only */
unsigned int ddr4_dll_dis_freq;
unsigned int phy_dll_dis_freq;
unsigned int ddr2_odt_dis_freq;
unsigned int phy_ddr2_odt_dis_freq;
unsigned int ddr2_drv;
unsigned int ddr2_odt;
unsigned int phy_ddr2_ca_drv;
unsigned int phy_ddr2_ck_drv;
unsigned int phy_ddr2_dq_drv;
unsigned int phy_ddr2_odt;
unsigned int ddr3_odt_dis_freq;
unsigned int phy_ddr3_odt_dis_freq;
unsigned int ddr3_drv;
unsigned int ddr3_odt;
unsigned int phy_ddr3_ca_drv;
unsigned int phy_ddr3_ck_drv;
unsigned int phy_ddr3_dq_drv;
unsigned int phy_ddr3_odt;
unsigned int phy_lpddr2_odt_dis_freq;
unsigned int lpddr2_drv;
unsigned int phy_lpddr2_ca_drv;
unsigned int phy_lpddr2_ck_drv;
unsigned int phy_lpddr2_dq_drv;
unsigned int phy_lpddr2_odt;
unsigned int lpddr3_odt_dis_freq;
unsigned int phy_lpddr3_odt_dis_freq;
unsigned int lpddr3_drv;
unsigned int lpddr3_odt;
unsigned int phy_lpddr3_ca_drv;
unsigned int phy_lpddr3_ck_drv;
unsigned int phy_lpddr3_dq_drv;
unsigned int phy_lpddr3_odt;
unsigned int lpddr4_odt_dis_freq;
unsigned int phy_lpddr4_odt_dis_freq;
unsigned int lpddr4_drv;
unsigned int lpddr4_dq_odt;
unsigned int lpddr4_ca_odt;
unsigned int phy_lpddr4_ca_drv;
unsigned int phy_lpddr4_ck_cs_drv;
unsigned int phy_lpddr4_dq_drv;
unsigned int phy_lpddr4_odt;
unsigned int ddr4_odt_dis_freq;
unsigned int phy_ddr4_odt_dis_freq;
unsigned int ddr4_drv;
unsigned int ddr4_odt;
unsigned int phy_ddr4_ca_drv;
unsigned int phy_ddr4_ck_drv;
unsigned int phy_ddr4_dq_drv;
unsigned int phy_ddr4_odt;
unsigned int available;
};
/* name rule: ddr4(pad_name)_ddr3_lpddr3_lpddr4_de-skew */
static const char * const rv1126_dts_ca_timing[] = {
"a0_a3_a3_cke1-a_de-skew",