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RK292X:modify DDR3 DLL disable frequency,part of the LVDDR3 can not

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work with low-frequency.
This commit is contained in:
cym
2013-03-22 21:01:11 +08:00
parent 1e778d3e93
commit 6a5987725d
1 changed files with 11 additions and 3 deletions
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14
arch/arm/mach-rk2928/ddr.c
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@@ -26,7 +26,7 @@
typedef uint32_t uint32 ;
#define DDR3_DDR2_DLL_DISABLE_FREQ (125) //lvddr3 Ƶ<><C6B5>̫<EFBFBD><CCAB>ʱdll<6C><6C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define DDR3_DDR2_DLL_DISABLE_FREQ (300)
#define DDR3_DDR2_ODT_DISABLE_FREQ (333)
#define SR_IDLE (0x1) //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
#define PD_IDLE (0x40) //unit:DDR clk cycle, and 0 for disable auto power-down
@@ -1187,8 +1187,16 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
{
tmp = 3;
}
cl = ddr3_cl_cwl[ddr_speed_bin][tmp] >> 16;
cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0x0ff;
if(nMHz < DDR3_DDR2_DLL_DISABLE_FREQ) //when dll bypss cl = cwl = 6;
{
cl = 6;
cwl = 6;
}
else
{
cl = ddr3_cl_cwl[ddr_speed_bin][tmp] >> 16;
cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0x0ff;
}
if(cl == 0)
{
ret = -4; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5>