Merge commit 'c1862eb07d904923cfbff4b91f51005e3195c4f4'

* commit 'c1862eb07d904923cfbff4b91f51005e3195c4f4': (35 commits) drm: rockchip: rk618: update hdmi connect status to jack drm: rockchip: rk618: add spdif for hdmi audio source misc: rk628: dsi: fix timing configuration not working phy: rockchip: phy-rockchip-usbdp: Fix typo in Rockchip copyright notice phy: rockchip: phy-rockchip-usb: Fix typo in Rockchip copyright notice phy: rockchip: phy-rockchip-typec: Fix typo in Rockchip copyright notice phy: rockchip: phy-rockchip-samsung-hdptx: Fix typo in Rockchip copyright notice phy: rockchip: phy-rockchip-pcie: Fix typo in Rockchip copyright notice phy: rockchip: phy-rockchip-inno-hdmi: Fix typo in Rockchip copyright notice phy: rockchip: phy-rockchip-inno-dsidphy: Fix typo in Rockchip copyright notice phy: rockchip: phy-rockchip-inno-csidphy: Fix typo in Rockchip copyright notice phy: rockchip: phy-rockchip-emmc: Fix typo in Rockchip copyright notice phy: rockchip: phy-rockchip-dp: Fix typo in Rockchip copyright notice PCI: rockchip: Fix typos in Rockchip copyright notices nvmem: rockchip-otp: Fix typo in Rockchip copyright notice nvmem: rockchip-efuse: Fix typo in Rockchip copyright notice nvmem: rockchip-secure-otp: Fix typos in Rockchip copyright notices ASoC: rockchip: rk3399_gru_sound: Fix typo in Rockchip copyright notice ASoC: rockchip: i2s: Fix typos in Rockchip copyright notices ASoC: rockchip: i2s-tdm: Fix typos in Rockchip copyright notices ... Change-Id: I379a3458f5672fbe4bbe20c6fa8a2de5cd103787
2026-06-05 10:31:46 +09:00 · 2025-01-21 20:04:01 +08:00
parent 10500a2d1f c1862eb07d
commit 6b33334fb6
49 changed files with 645 additions and 65 deletions
--- a/drivers/gpu/drm/rockchip/rk618/rk618_hdmi.c
+++ b/drivers/gpu/drm/rockchip/rk618/rk618_hdmi.c
@@ -440,6 +440,9 @@ struct rk618_hdmi {
 	struct switch_dev switchdev;
 #endif
 	struct rockchip_drm_sub_dev sub_dev;
+	hdmi_codec_plugged_cb plugged_cb;
+	struct device *codec_dev;
+	enum drm_connector_status last_connector_result;
 };

 enum {
@@ -545,6 +548,26 @@ static inline void hdmi_writeb(struct rk618_hdmi *hdmi, u16 offset, u32 val)
 	regmap_write(hdmi->regmap, (RK618_HDMI_BASE + ((offset) << 2)), val);
 }

+static void handle_plugged_change(struct rk618_hdmi *hdmi, bool plugged)
+{
+	if (hdmi->plugged_cb && hdmi->codec_dev)
+		hdmi->plugged_cb(hdmi->codec_dev, plugged);
+}
+
+static int rk618_hdmi_set_plugged_cb(struct rk618_hdmi *hdmi,
+				     hdmi_codec_plugged_cb fn,
+				     struct device *codec_dev)
+{
+	bool plugged;
+
+	hdmi->plugged_cb = fn;
+	hdmi->codec_dev = codec_dev;
+	plugged = hdmi->last_connector_result == connector_status_connected;
+	handle_plugged_change(hdmi, plugged);
+
+	return 0;
+}
+
 static void rk618_hdmi_set_polarity(struct rk618_hdmi *hdmi, int vic)
 {
 	u32 val, mask = HDMI_HSYNC_POL_INV | HDMI_VSYNC_POL_INV;
@@ -946,14 +969,23 @@ rk618_hdmi_connector_detect(struct drm_connector *connector, bool force)
 {
 	struct rk618_hdmi *hdmi = connector_to_hdmi(connector);
 	bool status;
+	enum drm_connector_status result;

 	status = rk618_hdmi_hpd_detect(hdmi);
 #ifdef CONFIG_SWITCH
 	switch_set_state(&hdmi->switchdev, status);
 #endif

-	return status ? connector_status_connected :
+	result = status ? connector_status_connected :
 			connector_status_disconnected;
+	if (result != hdmi->last_connector_result) {
+		dev_dbg(hdmi->dev, "rk618_hdmi read_hpd result: %d", result);
+		handle_plugged_change(hdmi,
+				result == connector_status_connected);
+		hdmi->last_connector_result = result;
+	}
+
+	return result;
 }

 static int rk618_hdmi_connector_get_modes(struct drm_connector *connector)
@@ -1133,8 +1165,9 @@ static const struct drm_bridge_funcs rk618_hdmi_bridge_funcs = {
 	.disable = rk618_hdmi_bridge_disable,
 };

-static int
-rk618_hdmi_audio_config_set(struct rk618_hdmi *hdmi, struct audio_info *audio)
+static int rk618_hdmi_audio_config_set(struct rk618_hdmi *hdmi,
+				       struct hdmi_codec_daifmt *daifmt,
+				       struct audio_info *audio)
 {
 	int rate, N, channel;

@@ -1182,14 +1215,19 @@ rk618_hdmi_audio_config_set(struct rk618_hdmi *hdmi, struct audio_info *audio)
 		return -ENOENT;
 	}

-	/* set_audio source I2S */
-	hdmi_writeb(hdmi, HDMI_AUDIO_CTRL1, 0x01);
+	if (daifmt->fmt == HDMI_SPDIF) {
+		/* set_audio source SPDIF */
+		hdmi_writeb(hdmi, HDMI_AUDIO_CTRL1, 0x09);
+	} else {
+		/* set_audio source I2S */
+		hdmi_writeb(hdmi, HDMI_AUDIO_CTRL1, 0x01);
+	}
 	hdmi_writeb(hdmi, AUDIO_SAMPLE_RATE, rate);
 	hdmi_writeb(hdmi, AUDIO_I2S_MODE, v_I2S_MODE(I2S_STANDARD) |
 		    v_I2S_CHANNEL(channel));

 	hdmi_writeb(hdmi, AUDIO_I2S_MAP, 0x00);
-	hdmi_writeb(hdmi, AUDIO_I2S_SWAPS_SPDIF, 0);
+	hdmi_writeb(hdmi, AUDIO_I2S_SWAPS_SPDIF, rate);

 	/* Set N value */
 	hdmi_writeb(hdmi, AUDIO_N_H, (N >> 16) & 0x0F);
@@ -1224,12 +1262,14 @@ static int rk618_hdmi_audio_hw_params(struct device *dev, void *d,
 	switch (daifmt->fmt) {
 	case HDMI_I2S:
 		break;
+	case HDMI_SPDIF:
+		break;
 	default:
 		dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
 		return -EINVAL;
 	}

-	return rk618_hdmi_audio_config_set(hdmi, &audio);
+	return rk618_hdmi_audio_config_set(hdmi, daifmt, &audio);
 }

 static void rk618_hdmi_audio_shutdown(struct device *dev, void *d)
@@ -1279,22 +1319,43 @@ static int rk618_hdmi_audio_get_eld(struct device *dev, void *d,
 	return ret;
 }

+static int rk618_hdmi_hook_plugged_cb(struct device *dev, void *data,
+				      hdmi_codec_plugged_cb fn,
+				      struct device *codec_dev)
+{
+	struct rk618_hdmi *hdmi = dev_get_drvdata(dev);
+
+	return rk618_hdmi_set_plugged_cb(hdmi, fn, codec_dev);
+}
+
 static const struct hdmi_codec_ops audio_codec_ops = {
 	.hw_params = rk618_hdmi_audio_hw_params,
 	.audio_shutdown = rk618_hdmi_audio_shutdown,
 	.mute_stream = rk618_hdmi_audio_mute_stream,
 	.get_eld = rk618_hdmi_audio_get_eld,
+	.hook_plugged_cb = rk618_hdmi_hook_plugged_cb,
 };

 static int rk618_hdmi_audio_codec_init(struct rk618_hdmi *hdmi,
 				       struct device *dev)
 {
+	const char *str = "i2s";
+	struct device_node *np = dev->of_node;
 	struct hdmi_codec_pdata codec_data = {
 		.i2s = 1,
+		.spdif = 0,
 		.ops = &audio_codec_ops,
 		.max_i2s_channels = 8,
 	};

+	if (of_property_read_string(np, "rockchip,format", &str))
+		dev_warn(dev, "can not get rockchip,format\n");
+
+	if (strstr(str, "spdif")) {
+		codec_data.i2s = 0;
+		codec_data.spdif = 1;
+	}
+
 	hdmi->audio_enable = false;
 	hdmi->audio_pdev = platform_device_register_data(dev,
 				HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_NONE,
--- a/drivers/misc/rk628/Makefile
+++ b/drivers/misc/rk628/Makefile
@@ -3,7 +3,7 @@
 rk628_misc-$(CONFIG_RK628_MISC) +=	rk628.o rk628_cru.o rk628_config.o rk628_post_process.o \
 					rk628_combrxphy.o rk628_hdmirx.o rk628_combtxphy.o rk628_dsi.o \
 					panel.o rk628_lvds.o rk628_rgb.o rk628_gvi.o rk628_pinctrl.o \
-					rk628_csi.o rk628_efuse.o
+					rk628_csi.o rk628_efuse.o rk628_pwm.o

 rk628_misc-$(CONFIG_RK628_MISC_HDMITX) += rk628_hdmitx.o

--- a/drivers/misc/rk628/panel.c
+++ b/drivers/misc/rk628/panel.c
@@ -164,14 +164,15 @@ int rk628_panel_info_get(struct rk628 *rk628, struct device_node *np)

 	backlight = of_parse_phandle(dev->of_node, "panel-backlight", 0);
 	if (backlight) {
-		panel->backlight = of_find_backlight_by_node(backlight);
-		of_node_put(backlight);
+		if (!rk628->pwm_bl_en) {
+			panel->backlight = of_find_backlight_by_node(backlight);
+			of_node_put(backlight);

-		if (!panel->backlight) {
-			dev_err(dev, "failed to find backlight\n");
-			return -EPROBE_DEFER;
+			if (!panel->backlight) {
+				dev_err(dev, "%s: failed to find backlight\n", __func__);
+				return -EPROBE_DEFER;
+			}
 		}
-
 	}

 	device_property_read_u32(dev, "panel-prepare-delay-ms", &panel->delay.prepare);
--- a/drivers/misc/rk628/rk628.c
+++ b/drivers/misc/rk628/rk628.c
@@ -31,6 +31,7 @@
 #include "rk628_hdmitx.h"
 #include "rk628_efuse.h"
 #include "rk628_config.h"
+#include "rk628_pwm.h"

 static const struct regmap_range rk628_cru_readable_ranges[] = {
 	regmap_reg_range(CRU_CPLL_CON0, CRU_CPLL_CON4),
@@ -586,6 +587,27 @@ static int rk628_fb_notifier_callback(struct notifier_block *nb,
 }
 #endif

+static int rk628_get_pwm_bl(struct rk628 *rk628)
+{
+	struct device_node *backlight;
+
+	backlight = of_parse_phandle(rk628->dev->of_node, "panel-backlight", 0);
+	if (backlight) {
+		rk628->panel->backlight = of_find_backlight_by_node(backlight);
+		of_node_put(backlight);
+
+		if (!rk628->panel->backlight) {
+			dev_err(rk628->dev, "%s: failed to find backlight\n", __func__);
+			return -EAGAIN;
+		}
+	} else {
+		dev_err(rk628->dev, "%s: failed to find panel-backlight\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static void rk628_display_work(struct work_struct *work)
 {
 	u8 ret = 0;
@@ -609,7 +631,22 @@ static void rk628_display_work(struct work_struct *work)
 	if (ret & HDMIRX_PLUGIN) {
 		/* if resolution or input format change, disable first */
 		rk628_display_disable(rk628);
-		rk628_display_enable(rk628);
+		if (rk628->pwm_bl_en && !rk628->panel->backlight) {
+			int bl_ret = 0;
+
+			bl_ret = rk628_get_pwm_bl(rk628);
+			if (!bl_ret) {
+				rk628_display_enable(rk628);
+			} else if (bl_ret == -EAGAIN) {
+				queue_delayed_work(rk628->monitor_wq,
+						   &rk628->delay_work, msecs_to_jiffies(50));
+				return;
+			} else {
+				return;
+			}
+		} else {
+			rk628_display_enable(rk628);
+		}
 	} else if (ret & HDMIRX_PLUGOUT) {
 		rk628_display_disable(rk628);
 	}
@@ -914,6 +951,19 @@ static int rk628_display_timings_get(struct rk628 *rk628)

 }

+static void rk628_pwm_work(struct work_struct *work)
+{
+	struct rk628 *rk628 = container_of(work, struct rk628, pwm_delay_work.work);
+	int ret;
+
+	ret = rk628_get_pwm_bl(rk628);
+	if (!ret)
+		rk628_display_enable(rk628);
+	else if (ret == -EAGAIN)
+		queue_delayed_work(rk628->pwm_wq, &rk628->pwm_delay_work,
+				   msecs_to_jiffies(50));
+}
+
 #define DEBUG_PRINT(args...) \
 		do { \
 			if (s) \
@@ -1377,6 +1427,7 @@ static void rk628_debugfs_create(struct rk628 *rk628)
 	rk628_mipi_dsi_create_debugfs_file(rk628);
 	rk628_gvi_create_debugfs_file(rk628);
 	rk628_hdmitx_create_debugfs_file(rk628);
+	rk628_pwm_create_debugfs_file(rk628);
 }

 static void rk628_loader_protect(struct rk628 *rk628)
@@ -1412,6 +1463,7 @@ rk628_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
 	struct rk628 *rk628;
 	int i, ret;
 	unsigned long irq_flags;
+	struct device_node *np;

 	rk628 = devm_kzalloc(dev, sizeof(*rk628), GFP_KERNEL);
 	if (!rk628)
@@ -1422,17 +1474,38 @@ rk628_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
 	i2c_set_clientdata(client, rk628);
 	rk628->hdmirx_irq = client->irq;

+	np = of_find_node_by_name(rk628->dev->of_node, "rk628-pwm");
+	if (of_device_is_available(np)) {
+		ret = rk628_pwm_probe(rk628, np);
+		if (ret) {
+			of_node_put(np);
+			dev_err(dev, "failed to probe pwm\n");
+			return ret;
+		}
+	}
+	of_node_put(np);
+
+	if (rk628->pwm_bl_en) {
+		rk628->pwm_wq = alloc_ordered_workqueue("%s",
+			WQ_MEM_RECLAIM | WQ_FREEZABLE, "rk628-pwm-wq");
+		if (!rk628->pwm_wq)
+			return -ENOMEM;
+
+		INIT_DELAYED_WORK(&rk628->pwm_delay_work, rk628_pwm_work);
+	}
+
 	ret = rk628_display_route_info_parse(rk628);
 	if (ret) {
-		dev_err(dev, "display route parse err\n");
-		return ret;
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "display route err\n");
+		goto destroy_pwm_wq;
 	}

 	if (!rk628_output_is_csi(rk628)) {
 		ret = rk628_display_timings_get(rk628);
 		if (ret && !rk628_output_is_hdmi(rk628)) {
 			dev_info(dev, "display timings err\n");
-			return ret;
+			goto destroy_pwm_wq;
 		}
 	}

@@ -1443,7 +1516,7 @@ rk628_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
 	if (IS_ERR(rk628->soc_24M)) {
 		ret = PTR_ERR(rk628->soc_24M);
 		dev_err(dev, "Unable to get soc_24M: %d\n", ret);
-		return ret;
+		goto destroy_pwm_wq;
 	}

 	clk_prepare_enable(rk628->soc_24M);
@@ -1518,6 +1591,8 @@ rk628_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
 		INIT_DELAYED_WORK(&rk628->dsi_delay_work, rk628_dsi_work);
 	}

+	rk628_pwm_init(rk628);
+
 	rk628_cru_init(rk628);

 	if (rk628_output_is_csi(rk628))
@@ -1566,7 +1641,11 @@ rk628_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
 					    msecs_to_jiffies(50));
 		}
 	} else {
-		rk628_display_enable(rk628);
+		if (rk628->pwm_bl_en)
+			queue_delayed_work(rk628->pwm_wq, &rk628->pwm_delay_work,
+					   msecs_to_jiffies(50));
+		else
+			rk628_display_enable(rk628);
 	}

 	pm_runtime_enable(dev);
@@ -1576,6 +1655,11 @@ rk628_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)

 err_clk:
 	clk_disable_unprepare(rk628->soc_24M);
+
+destroy_pwm_wq:
+	if (rk628->pwm_wq)
+		destroy_workqueue(rk628->pwm_wq);
+
 	return ret;
 }

@@ -1601,6 +1685,9 @@ static int rk628_i2c_remove(struct i2c_client *client)
 	rk628_set_hdmirx_irq(rk628, GRF_INTR0_EN, false);
 	cancel_delayed_work_sync(&rk628->delay_work);
 	destroy_workqueue(rk628->monitor_wq);
+	cancel_delayed_work_sync(&rk628->pwm_delay_work);
+	destroy_workqueue(rk628->pwm_wq);
+	put_device(&rk628->panel->backlight->dev);
 	pm_runtime_disable(dev);
 	clk_disable_unprepare(rk628->soc_24M);
 #if KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
--- a/drivers/misc/rk628/rk628.h
+++ b/drivers/misc/rk628/rk628.h
@@ -18,6 +18,7 @@
 #include <linux/wakelock.h>
 #include <linux/workqueue.h>
 #include <linux/regulator/consumer.h>
+#include <linux/pwm.h>

 #define DRIVER_VERSION				"0.1.0"
 #define UPDATE(x, h, l)		(((x) << (l)) & GENMASK((h), (l)))
@@ -223,6 +224,11 @@
 #define GRF_OS_REG1			0x0144
 #define GRF_OS_REG2			0x0148
 #define GRF_OS_REG3			0x014c
+#define GRF_PWM_PERIOD			0x0150
+#define GRF_PWM_DUTY			0x0154
+#define GRF_PWM_CTRL			0x0158
+#define GRF_PWM_CH_CNT			0x015c
+#define GRF_PWM_STATUS			0x0160
 #define GRF_RGB_RX_DBG_MEAS0		0x0170
 #define RGB_RX_EVAL_TIME_MASK		GENMASK(27, 16)
 #define RGB_RX_MODET_EN			BIT(1)
@@ -547,6 +553,15 @@ struct rk628_rgb {
 	bool bt1120_uv_swap;
 };

+struct rk628_pwm {
+	struct pwm_chip chip;
+	unsigned long clk_rate;
+	bool center_aligned;
+	bool oneshot_en;
+	bool is_output_m1;
+	int irq;
+};
+
 struct rk628 {
 	struct device *dev;
 	struct i2c_client *client;
@@ -578,12 +593,16 @@ struct rk628 {
 	struct rk628_lvds lvds;
 	struct rk628_gvi gvi;
 	struct rk628_combtxphy combtxphy;
+	struct rk628_pwm pwm;
 	int sync_pol;
 	void *csi;
 	struct notifier_block fb_nb;
 	u32 version;
 	struct rk628_rgb rgb;
 	int old_blank;
+	struct workqueue_struct *pwm_wq;
+	struct delayed_work pwm_delay_work;
+	bool pwm_bl_en;
 };

 static inline bool rk628_input_is_hdmi(struct rk628 *rk628)
--- a/drivers/misc/rk628/rk628_dsi.c
+++ b/drivers/misc/rk628/rk628_dsi.c
@@ -984,6 +984,10 @@ static void mipi_dphy_set_timing(const struct rk628_dsi *dsi)
 	};
 	unsigned int index;

+	// These ranges use the controller's internal automatically calculated timing.
+	if (dsi->lane_mbps < 800 || (dsi->lane_mbps >= 900 && dsi->lane_mbps < 1100))
+		return;
+
 	if (dsi->lane_mbps < timing_table[0].min_lane_mbps)
 		return;

@@ -995,9 +999,6 @@ static void mipi_dphy_set_timing(const struct rk628_dsi *dsi)
 	if (index == ARRAY_SIZE(timing_table))
 		--index;

-	if (dsi->lane_mbps < timing_table[index].max_lane_mbps)
-		return;
-
 	testif_set_timing(dsi, 0x60, 0x3f, timing_table[index].clk_lp);
 	testif_set_timing(dsi, 0x61, 0x7f, timing_table[index].clk_hs_prepare);
 	testif_set_timing(dsi, 0x62, 0x3f, timing_table[index].clk_hs_zero);
--- a/drivers/misc/rk628/rk628_hdmirx.c
+++ b/drivers/misc/rk628/rk628_hdmirx.c
@@ -363,7 +363,8 @@ static void rk628_hdmirx_delayed_work_audio(struct work_struct *work)
 	}
 	audio_state->pre_state = fifo_status;
 exit:
-	schedule_delayed_work(&hdmirx->delayed_work_audio, msecs_to_jiffies(delay));
+	queue_delayed_work(system_freezable_wq, &hdmirx->delayed_work_audio,
+			   msecs_to_jiffies(delay));
 }

 static void rk628_hdmirx_audio_setup(struct rk628 *rk628)
@@ -417,7 +418,8 @@ static void rk628_hdmirx_audio_setup(struct rk628 *rk628)
 	rk628_i2c_write(rk628, HDMI_RX_AUD_CHEXTR_CTRL, AUD_LAYOUT_CTRL(1));
 	/* audio detect */
 	rk628_i2c_write(rk628, HDMI_RX_PDEC_AUDIODET_CTRL, AUDIODET_THRESHOLD(0));
-	schedule_delayed_work(&hdmirx->delayed_work_audio, msecs_to_jiffies(1000));
+	queue_delayed_work(system_freezable_wq, &hdmirx->delayed_work_audio,
+			   msecs_to_jiffies(1000));
 }

 static void rk628_hdmirx_ctrl_enable(struct rk628 *rk628)
--- a/drivers/misc/rk628/rk628_pwm.c
+++ b/drivers/misc/rk628/rk628_pwm.c
@@ -0,0 +1,393 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ * Author: Lingsong Ding <damon.ding@rock-chips.com>
+ */
+
+#include <linux/debugfs.h>
+#include <linux/platform_device.h>
+#include "rk628.h"
+#include "rk628_cru.h"
+#include "rk628_gpio.h"
+#include "rk628_pwm.h"
+
+#define PWM_ENABLE		(1 << 0)
+#define PWM_MODE_SHIFT		1
+#define PWM_MODE_MASK		(0x3 << PWM_MODE_SHIFT)
+#define PWM_ONESHOT		(0 << PWM_MODE_SHIFT)
+#define PWM_CONTINUOUS		(1 << PWM_MODE_SHIFT)
+#define PWM_DUTY_POSITIVE	(1 << 3)
+#define PWM_DUTY_NEGATIVE	(0 << 3)
+#define PWM_INACTIVE_NEGATIVE	(0 << 4)
+#define PWM_INACTIVE_POSITIVE	(1 << 4)
+#define PWM_POLARITY_MASK	(PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
+#define PWM_OUTPUT_LEFT		(0 << 5)
+#define PWM_OUTPUT_CENTER	(1 << 5)
+#define PWM_LP_DISABLE		(0 << 8)
+#define PWM_CLK_SEL_SHIFT	9
+#define PWM_CLK_SEL_MASK	(1 << PWM_CLK_SEL_SHIFT)
+#define PWM_SEL_NO_SCALED_CLOCK	(0 << PWM_CLK_SEL_SHIFT)
+#define PWM_SEL_SCALED_CLOCK	(1 << PWM_CLK_SEL_SHIFT)
+#define PWM_PRESCELE_SHIFT	12
+#define PWM_PRESCALE_MASK	(0x3 << PWM_PRESCELE_SHIFT)
+#define PWM_SCALE_SHIFT		16
+#define PWM_SCALE_MASK		(0xff << PWM_SCALE_SHIFT)
+
+#define PWM_ONESHOT_COUNT_SHIFT	24
+#define PWM_ONESHOT_COUNT_MASK	(0xff << PWM_ONESHOT_COUNT_SHIFT)
+#define PWM_ONESHOT_COUNT_MAX	256
+
+#define PWM_EN_CLR_SHIFT	2
+#define PWM_EN_CLR		(1 << PWM_EN_CLR_SHIFT)
+#define PWM_INT_SET_SHIFT	3
+
+#define PWM_ENABLE_CONF		(PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | PWM_CONTINUOUS)
+#define PWM_ENABLE_CONF_MASK	(GENMASK(2, 0) | BIT(5) | BIT(8))
+
+#define PWM_DCLK_RATE		24000000
+
+#define DEBUG_PRINT(args...) \
+		do { \
+			if (s) \
+				seq_printf(s, args); \
+			else \
+				pr_info(args); \
+		} while (0)
+
+static inline struct rk628 *to_rk628(struct rk628_pwm *p)
+{
+	return container_of(p, struct rk628, pwm);
+}
+
+static inline struct rk628_pwm *to_rk628_pwm(struct pwm_chip *pc)
+{
+	return container_of(pc, struct rk628_pwm, chip);
+}
+
+static void rk628_pwm_dclk_enable(struct rk628 *rk628)
+{
+}
+
+static void rk628_pwm_dclk_disable(struct rk628 *rk628)
+{
+}
+
+#if KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
+static void rk628_pwm_get_state(struct pwm_chip *chip,
+				struct pwm_device *pwm,
+				struct pwm_state *state)
+#else
+static int rk628_pwm_get_state(struct pwm_chip *chip,
+			       struct pwm_device *pwm,
+			       struct pwm_state *state)
+#endif
+{
+	struct rk628_pwm *p = to_rk628_pwm(chip);
+	struct rk628 *rk628 = to_rk628(p);
+	u32 enable_conf = PWM_ENABLE_CONF;
+	u32 val;
+	u32 dclk_div;
+	u64 tmp;
+
+	dclk_div = p->oneshot_en ? 2 : 1;
+
+	rk628_i2c_read(rk628, GRF_PWM_PERIOD, &val);
+	tmp = val * dclk_div * NSEC_PER_SEC;
+	state->period = DIV_ROUND_CLOSEST_ULL(tmp, p->clk_rate);
+
+	rk628_i2c_read(rk628, GRF_PWM_DUTY, &val);
+	tmp = val * dclk_div * NSEC_PER_SEC;
+	state->duty_cycle =  DIV_ROUND_CLOSEST_ULL(tmp, p->clk_rate);
+
+	rk628_i2c_read(rk628, GRF_PWM_CTRL, &val);
+	if (p->oneshot_en)
+		enable_conf &= ~PWM_CONTINUOUS;
+	state->enabled = (val & enable_conf) == enable_conf;
+
+	if (!(val & PWM_DUTY_POSITIVE))
+		state->polarity = PWM_POLARITY_INVERSED;
+	else
+		state->polarity = PWM_POLARITY_NORMAL;
+#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE
+	return 0;
+#endif
+}
+
+static void rk628_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+				const struct pwm_state *state)
+{
+	struct rk628_pwm *p = to_rk628_pwm(chip);
+	struct rk628 *rk628 = to_rk628(p);
+	unsigned long period, duty;
+	u64 div;
+	u32 ctrl;
+	u8 dclk_div = 1;
+
+#ifdef CONFIG_PWM_ROCKCHIP_ONESHOT
+	if (state->oneshot_count > 0 && state->oneshot_count <= PWM_ONESHOT_COUNT_MAX)
+		dclk_div = 2;
+#endif
+
+	/*
+	 * Since period and duty cycle registers have a width of 32
+	 * bits, every possible input period can be obtained using the
+	 * default prescaler value for all practical clock rate values.
+	 */
+	div = (u64)p->clk_rate * state->period;
+	period = DIV_ROUND_CLOSEST_ULL(div, dclk_div * NSEC_PER_SEC);
+
+	div = (u64)p->clk_rate * state->duty_cycle;
+	duty = DIV_ROUND_CLOSEST_ULL(div, dclk_div * NSEC_PER_SEC);
+
+	/*
+	 * Lock the period and duty of previous configuration, then
+	 * change the duty and period, that would not be effective.
+	 */
+	rk628_i2c_read(rk628, GRF_PWM_CTRL, &ctrl);
+
+#ifdef CONFIG_PWM_ROCKCHIP_ONESHOT
+	if (state->oneshot_count > 0 && state->oneshot_count <= PWM_ONESHOT_COUNT_MAX) {
+		u32 int_ctrl;
+
+		/*
+		 * This is a workaround, an uncertain waveform will be
+		 * generated after oneshot ends. It is needed to enable
+		 * the dclk scale function to resolve it. It doesn't
+		 * matter what the scale factor is, just make sure the
+		 * scale function is turned on, for which we set scale
+		 * factor to 2.
+		 */
+		ctrl &= ~PWM_SCALE_MASK;
+		ctrl |= (dclk_div / 2) << PWM_SCALE_SHIFT;
+		ctrl &= ~PWM_CLK_SEL_MASK;
+		ctrl |= PWM_SEL_SCALED_CLOCK;
+
+		p->oneshot_en = true;
+		ctrl &= ~PWM_MODE_MASK;
+		ctrl |= PWM_ONESHOT;
+
+		ctrl &= ~PWM_ONESHOT_COUNT_MASK;
+		ctrl |= (state->oneshot_count - 1) << PWM_ONESHOT_COUNT_SHIFT;
+
+		rk628_i2c_read(rk628, GRF_PWM_STATUS, &int_ctrl);
+		int_ctrl |= PWM_EN_CLR;
+		rk628_i2c_write(rk628, GRF_PWM_STATUS, int_ctrl);
+	} else {
+		u32 int_ctrl;
+
+		ctrl &= ~PWM_SCALE_MASK;
+		ctrl &= ~PWM_CLK_SEL_MASK;
+		ctrl |= PWM_SEL_NO_SCALED_CLOCK;
+
+		if (state->oneshot_count)
+			dev_err(chip->dev, "Oneshot_count must be between 1 and 256.\n");
+
+		p->oneshot_en = false;
+		ctrl &= ~PWM_MODE_MASK;
+		ctrl |= PWM_CONTINUOUS;
+
+		ctrl &= ~PWM_ONESHOT_COUNT_MASK;
+
+		rk628_i2c_read(rk628, GRF_PWM_STATUS, &int_ctrl);
+		int_ctrl &= ~PWM_EN_CLR;
+		rk628_i2c_write(rk628, GRF_PWM_STATUS, int_ctrl);
+	}
+#endif
+
+	rk628_i2c_write(rk628, GRF_PWM_PERIOD, period);
+	rk628_i2c_write(rk628, GRF_PWM_DUTY, duty);
+
+	ctrl &= ~PWM_POLARITY_MASK;
+	if (state->polarity == PWM_POLARITY_INVERSED)
+		ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
+	else
+		ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
+
+	rk628_i2c_write(rk628, GRF_PWM_CTRL, ctrl);
+}
+
+static int rk628_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, bool enable)
+{
+	struct rk628_pwm *p = to_rk628_pwm(chip);
+	struct rk628 *rk628 = to_rk628(p);
+	u32 val;
+
+	if (enable)
+		rk628_pwm_dclk_enable(rk628);
+
+	rk628_i2c_read(rk628, GRF_PWM_CTRL, &val);
+	val &= ~PWM_ENABLE_CONF_MASK;
+
+	if (p->center_aligned)
+		val |= PWM_OUTPUT_CENTER;
+
+	if (enable) {
+		val |= PWM_ENABLE_CONF;
+		if (p->oneshot_en)
+			val &= ~PWM_CONTINUOUS;
+	} else {
+		val &= ~PWM_ENABLE_CONF;
+	}
+
+	rk628_i2c_write(rk628, GRF_PWM_CTRL, val);
+
+	if (!enable)
+		rk628_pwm_dclk_disable(rk628);
+
+	return 0;
+}
+
+static void rk628_pwm_set_iomux(struct pwm_chip *chip)
+{
+	struct rk628_pwm *p = to_rk628_pwm(chip);
+	struct rk628 *rk628 = to_rk628(p);
+
+	/*
+	 * The pwm output iomux:
+	 * m0: gpio3b4
+	 * m1: gpio0a6
+	 */
+	if (p->is_output_m1) {
+		rk628_i2c_write(rk628, GRF_GPIO0AB_SEL_CON, 0x03000300);
+		rk628_i2c_write(rk628, RK628_GPIO0_BASE + GPIO_SWPORT_DDR_L, 0x00400040);
+	} else {
+		rk628_i2c_write(rk628, GRF_GPIO3AB_SEL_CON, 0x30003000);
+		rk628_i2c_write(rk628, RK628_GPIO3_BASE + GPIO_SWPORT_DDR_L, 0x10001000);
+	}
+}
+
+static int rk628_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+			   const struct pwm_state *state)
+{
+	struct pwm_state curstate;
+	bool enabled;
+	int ret = 0;
+
+	pwm_get_state(pwm, &curstate);
+	enabled = curstate.enabled;
+
+	if (state->polarity != curstate.polarity && enabled) {
+		ret = rk628_pwm_enable(chip, pwm, false);
+		if (ret)
+			goto out;
+		enabled = false;
+	}
+
+	rk628_pwm_config(chip, pwm, state);
+	if (state->enabled != enabled) {
+		ret = rk628_pwm_enable(chip, pwm, state->enabled);
+		if (ret)
+			goto out;
+	}
+
+	if (state->enabled)
+		rk628_pwm_set_iomux(chip);
+
+out:
+	return ret;
+}
+
+static const struct pwm_ops rk628_pwm_ops = {
+	.get_state = rk628_pwm_get_state,
+	.apply = rk628_pwm_apply,
+	.owner = THIS_MODULE,
+};
+
+int rk628_pwm_probe(struct rk628 *rk628, struct device_node *pwm_np)
+{
+	struct pwm_chip *chip = &rk628->pwm.chip;
+	struct platform_device *pd;
+	int ret;
+
+	pd = platform_device_alloc("rk628-pwm", -1);
+	if (!pd) {
+		dev_err(rk628->dev, "failed to alloc pwm platform device\n");
+		return -EINVAL;
+	}
+
+	ret = platform_device_add(pd);
+	if (ret) {
+		dev_err(rk628->dev, "failed to add pwm platform device\n");
+		return -EINVAL;
+	}
+
+	chip->dev = &pd->dev;
+	chip->dev->of_node = pwm_np;
+	chip->ops = &rk628_pwm_ops;
+	chip->base = -1;
+	chip->npwm = 1;
+	chip->of_xlate = of_pwm_xlate_with_flags;
+	chip->of_pwm_n_cells = 3;
+
+	rk628->pwm.clk_rate = PWM_DCLK_RATE;
+
+	rk628->pwm.center_aligned = of_property_read_bool(pwm_np, "pwm,center-aligned");
+	rk628->pwm.is_output_m1 = of_property_read_bool(pwm_np, "pwm,output-m1");
+	rk628->pwm_bl_en = of_property_read_bool(pwm_np, "pwm,backlight");
+
+	ret = pwmchip_add(chip);
+	if (ret < 0) {
+		dev_err(rk628->dev, "pwmchip_add() failed: %d\n", ret);
+		return ret;
+	}
+
+	/*
+	 * To avoid warning in devm_pwm_get() process.
+	 */
+	pd->dev.links.status = DL_DEV_PROBING;
+
+	return 0;
+}
+
+void rk628_pwm_init(struct rk628 *rk628)
+{
+	u32 ctrl;
+	bool enabled;
+
+	rk628_i2c_read(rk628, GRF_PWM_CTRL, &ctrl);
+	enabled = (ctrl & PWM_ENABLE_CONF) == PWM_ENABLE_CONF;
+	if (!enabled)
+		rk628_pwm_dclk_disable(rk628);
+}
+
+static int rk628_debugfs_pwm_regs_dump(struct seq_file *s, void *data)
+{
+	struct rk628 *rk628 = s->private;
+	u32 val;
+
+	DEBUG_PRINT("pwm regs:\n");
+	rk628_i2c_read(rk628, GRF_PWM_PERIOD, &val);
+	DEBUG_PRINT("period: 0x%08x\n", val);
+	rk628_i2c_read(rk628, GRF_PWM_DUTY, &val);
+	DEBUG_PRINT("duty:   0x%08x\n", val);
+	rk628_i2c_read(rk628, GRF_PWM_CTRL, &val);
+	DEBUG_PRINT("ctrl:   0x%08x\n", val);
+	rk628_i2c_read(rk628, GRF_PWM_CH_CNT, &val);
+	DEBUG_PRINT("ch_cnt: 0x%08x\n", val);
+	rk628_i2c_read(rk628, GRF_PWM_STATUS, &val);
+	DEBUG_PRINT("status: 0x%08x\n", val);
+
+	return 0;
+}
+
+static int rk628_debugfs_pwm_regs_open(struct inode *inode, struct file *file)
+{
+	struct rk628 *rk628 = inode->i_private;
+
+	return single_open(file, rk628_debugfs_pwm_regs_dump, rk628);
+}
+
+static const struct file_operations rk628_debugfs_pwm_regs_fops = {
+	.owner = THIS_MODULE,
+	.open = rk628_debugfs_pwm_regs_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+void rk628_pwm_create_debugfs_file(struct rk628 *rk628)
+{
+	debugfs_create_file("pwm_regs", 0400, rk628->debug_dir, rk628,
+			    &rk628_debugfs_pwm_regs_fops);
+}
--- a/drivers/misc/rk628/rk628_pwm.h
+++ b/drivers/misc/rk628/rk628_pwm.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ * Author: Lingsong Ding <damon.ding@rock-chips.com>
+ */
+
+#ifndef RK628_PWM_H
+#define RK628_PWM_H
+#include "rk628.h"
+
+int rk628_pwm_probe(struct rk628 *rk628, struct device_node *pwm_np);
+void rk628_pwm_init(struct rk628 *rk628);
+void rk628_pwm_create_debugfs_file(struct rk628 *rk628);
+
+#endif
--- a/drivers/nvmem/rockchip-efuse.c
+++ b/drivers/nvmem/rockchip-efuse.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip eFuse Driver
 *
- * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2015 Rockchip Electronics Co., Ltd.
 * Author: Caesar Wang <wxt@rock-chips.com>
 */

--- a/drivers/nvmem/rockchip-otp.c
+++ b/drivers/nvmem/rockchip-otp.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip OTP Driver
 *
- * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2018 Rockchip Electronics Co., Ltd.
 * Author: Finley Xiao <finley.xiao@rock-chips.com>
 */

--- a/drivers/nvmem/rockchip-secure-otp.c
+++ b/drivers/nvmem/rockchip-secure-otp.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip Secure OTP Driver
 *
- * Copyright (c) 2023 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
 * Author: Hisping <hisping.lin@rock-chips.com>
 */

--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip AXI PCIe endpoint controller driver
 *
- * Copyright (c) 2018 Rockchip, Inc.
+ * Copyright (c) 2018 Rockchip Electronics Co., Ltd.
 *
 * Author: Shawn Lin <shawn.lin@rock-chips.com>
 *         Simon Xue <xxm@rock-chips.com>
--- a/drivers/pci/controller/pcie-rockchip-host.c
+++ b/drivers/pci/controller/pcie-rockchip-host.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip AXI PCIe host controller driver
 *
- * Copyright (c) 2016 Rockchip, Inc.
+ * Copyright (c) 2016 Rockchip Electronics Co., Ltd.
 *
 * Author: Shawn Lin <shawn.lin@rock-chips.com>
 *         Wenrui Li <wenrui.li@rock-chips.com>
--- a/drivers/pci/controller/pcie-rockchip.c
+++ b/drivers/pci/controller/pcie-rockchip.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip AXI PCIe host controller driver
 *
- * Copyright (c) 2016 Rockchip, Inc.
+ * Copyright (c) 2016 Rockchip Electronics Co., Ltd.
 *
 * Author: Shawn Lin <shawn.lin@rock-chips.com>
 *         Wenrui Li <wenrui.li@rock-chips.com>
--- a/drivers/pci/controller/pcie-rockchip.h
+++ b/drivers/pci/controller/pcie-rockchip.h
@@ -2,7 +2,7 @@
 /*
 * Rockchip AXI PCIe controller driver
 *
- * Copyright (c) 2018 Rockchip, Inc.
+ * Copyright (c) 2018 Rockchip Electronics Co., Ltd.
 *
 * Author: Shawn Lin <shawn.lin@rock-chips.com>
 *
--- a/drivers/phy/rockchip/phy-rockchip-dp.c
+++ b/drivers/phy/rockchip/phy-rockchip-dp.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip DP PHY driver
 *
- * Copyright (C) 2016 FuZhou Rockchip Co., Ltd.
+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
 * Author: Yakir Yang <ykk@@rock-chips.com>
 */

--- a/drivers/phy/rockchip/phy-rockchip-emmc.c
+++ b/drivers/phy/rockchip/phy-rockchip-emmc.c
@@ -3,7 +3,7 @@
 * Rockchip emmc PHY driver
 *
 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
- * Copyright (C) 2016 ROCKCHIP, Inc.
+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
 */

 #include <linux/clk.h>
--- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip MIPI RX Innosilicon DPHY driver
 *
- * Copyright (C) 2021 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
 */

 #include <linux/bitfield.h>
--- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2018 Rockchip Electronics Co., Ltd.
 *
 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
 */
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd.
 *
 * Author: Zheng Yang <zhengyang@rock-chips.com>
 *         Heiko Stuebner <heiko@sntech.de>
--- a/drivers/phy/rockchip/phy-rockchip-inno-video-phy.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-video-phy.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2018 Rockchip Electronics Co., Ltd.
 *
 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
 */
--- a/drivers/phy/rockchip/phy-rockchip-pcie.c
+++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
@@ -3,7 +3,7 @@
 * Rockchip PCIe PHY driver
 *
 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
- * Copyright (C) 2016 ROCKCHIP, Inc.
+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
 */

 #include <linux/clk.h>
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip HDMI/DP Combo PHY with Samsung IP block
 *
- * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
 */

 #include <linux/bitfield.h>
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Copyright (C) Rockchip Electronics Co., Ltd.
 * Author: Chris Zhong <zyw@rock-chips.com>
 *         Kever Yang <kever.yang@rock-chips.com>
 *
--- a/drivers/phy/rockchip/phy-rockchip-usb.c
+++ b/drivers/phy/rockchip/phy-rockchip-usb.c
@@ -3,7 +3,7 @@
 * Rockchip usb PHY driver
 *
 * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
- * Copyright (C) 2014 ROCKCHIP, Inc.
+ * Copyright (C) 2014 Rockchip Electronics Co., Ltd.
 */

 #include <linux/clk.h>
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip USBDP Combo PHY with Samsung IP block driver
 *
- * Copyright (C) 2021 Rockchip Electronics Co., Ltd
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
 */

 #include <linux/bitfield.h>
--- a/drivers/rpmsg/rockchip_rpmsg_mbox.c
+++ b/drivers/rpmsg/rockchip_rpmsg_mbox.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip Remote Processors Messaging Platform Support.
 *
- * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 * Author: Steven Liu <steven.liu@rock-chips.com>
 */

--- a/drivers/rpmsg/rockchip_rpmsg_softirq.c
+++ b/drivers/rpmsg/rockchip_rpmsg_softirq.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip Remote Processors Messaging Platform Support.
 *
- * Copyright (c) 2023 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
 * Author: Hongming Zou <hongming.zou@rock-chips.com>
 */

--- a/drivers/rpmsg/rockchip_rpmsg_test.c
+++ b/drivers/rpmsg/rockchip_rpmsg_test.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip Remote Processors Messaging Test.
 *
- * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 * Author: Hongming Zou <hongming.zou@rock-chips.com>
 */

--- a/drivers/rtc/rtc-rk630.c
+++ b/drivers/rtc/rtc-rk630.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2023 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
 */
 #include <linux/bcd.h>
 #include <linux/kernel.h>
--- a/drivers/rtc/rtc-rockchip.c
+++ b/drivers/rtc/rtc-rockchip.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2022 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 */
 #include <linux/bcd.h>
 #include <linux/kernel.h>
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip Generic power domain support.
 *
- * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
+ * Copyright (c) 2015 Rockchip Electronics Co., Ltd.
 */

 #include <linux/module.h>
--- a/drivers/ufs/host/ufs-rockchip.c
+++ b/drivers/ufs/host/ufs-rockchip.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip UFS Host Controller driver
 *
- * Copyright (C) 2024 Rockchip Electronics Co.Ltd.
+ * Copyright (C) 2024 Rockchip Electronics Co., Ltd.
 */

 #include <linux/clk.h>
--- a/drivers/ufs/host/ufs-rockchip.h
+++ b/drivers/ufs/host/ufs-rockchip.h
@@ -2,7 +2,7 @@
 /*
 * Rockchip UFS Host Controller driver
 *
- * Copyright (C) 2024 Rockchip Electronics Co.Ltd.
+ * Copyright (C) 2024 Rockchip Electronics Co., Ltd.
 */

 #ifndef _UFS_ROCKCHIP_H_
--- a/include/linux/rockchip/nvmem.h
+++ b/include/linux/rockchip/nvmem.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2023 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
 * Author: Hisping <hisping.lin@rock-chips.com>
 */
 #ifndef __ROCKCHIP_NVMEM_H
--- a/mm/cma_debug_bitmap_hex.c
+++ b/mm/cma_debug_bitmap_hex.c
@@ -4,7 +4,7 @@
 *
 * Copyright (c) 2015 Sasha Levin <sasha.levin@oracle.com>
 *
- * Copyright (C) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
 *
 */

--- a/net/rfkill/rfkill-bt.c
+++ b/net/rfkill/rfkill-bt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 ROCKCHIP, Inc.
+ * Copyright (C) 2012 Rockchip Electronics Co., Ltd.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
--- a/net/rfkill/rfkill-wlan.c
+++ b/net/rfkill/rfkill-wlan.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 ROCKCHIP, Inc.
+ * Copyright (C) 2012 Rockchip Electronics Co., Ltd.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
--- a/scripts/mkkrnlimg.c
+++ b/scripts/mkkrnlimg.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * (C) Copyright Fuzhou Rockchip Electronics Co., Ltd
+ * (C) Copyright Rockchip Electronics Co., Ltd.
 */

 #include <stdint.h>
--- a/sound/soc/rockchip/rk3399_gru_sound.c
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip machine ASoC driver for boards using MAX98357A/RT5514/DA7219
 *
- * Copyright (c) 2016, ROCKCHIP CORPORATION.  All rights reserved.
+ * Copyright (c) 2016, Rockchip Electronics Co., Ltd. All rights reserved.
 */

 #include <linux/module.h>
--- a/sound/soc/rockchip/rockchip_i2s.c
+++ b/sound/soc/rockchip/rockchip_i2s.c
@@ -3,7 +3,7 @@
 *
 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
 *
- * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2014 Rockchip Electronics Co., Ltd.
 * Author: Jianqun <jay.xu@rock-chips.com>
 */

--- a/sound/soc/rockchip/rockchip_i2s.h
+++ b/sound/soc/rockchip/rockchip_i2s.h
@@ -4,7 +4,7 @@
 *
 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
 *
- * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2014 Rockchip Electronics Co., Ltd.
 * Author: Jianqun xu <jay.xu@rock-chips.com>
 */

--- a/sound/soc/rockchip/rockchip_i2s_tdm.c
+++ b/sound/soc/rockchip/rockchip_i2s_tdm.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver

-// Copyright (c) 2018 Rockchip Electronics Co. Ltd.
+// Copyright (c) 2018 Rockchip Electronics Co., Ltd.
 // Author: Sugar Zhang <sugar.zhang@rock-chips.com>
 // Author: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>

--- a/sound/soc/rockchip/rockchip_i2s_tdm.h
+++ b/sound/soc/rockchip/rockchip_i2s_tdm.h
@@ -2,7 +2,7 @@
 /*
 * ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
 *
- * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2018 Rockchip Electronics Co., Ltd.
 * Author: Sugar Zhang <sugar.zhang@rock-chips.com>
 *
 */
--- a/sound/soc/rockchip/rockchip_max98090.c
+++ b/sound/soc/rockchip/rockchip_max98090.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip machine ASoC driver for boards using a MAX90809 CODEC.
 *
- * Copyright (c) 2014, ROCKCHIP CORPORATION.  All rights reserved.
+ * Copyright (c) 2014, Rockchip Electronics Co., Ltd. All rights reserved.
 */

 #include <linux/module.h>
--- a/sound/soc/rockchip/rockchip_rt5645.c
+++ b/sound/soc/rockchip/rockchip_rt5645.c
@@ -2,7 +2,7 @@
 /*
 * Rockchip machine ASoC driver for boards using a RT5645/RT5650 CODEC.
 *
- * Copyright (c) 2015, ROCKCHIP CORPORATION.  All rights reserved.
+ * Copyright (c) 2015, Rockchip Electronics Co., Ltd. All rights reserved.
 */

 #include <linux/module.h>
--- a/sound/soc/rockchip/rockchip_spdif.c
+++ b/sound/soc/rockchip/rockchip_spdif.c
@@ -3,7 +3,7 @@
 *
 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
 *
- * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2014 Rockchip Electronics Co., Ltd.
 * Author: Jianqun <jay.xu@rock-chips.com>
 * Copyright (c) 2015 Collabora Ltd.
 * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
--- a/tools/testing/selftests/rkpinctrl/iomux.c
+++ b/tools/testing/selftests/rkpinctrl/iomux.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 */

 #include <errno.h>