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[ARM] tegra: Enable pl310 data prefetching and prefetch offset

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Enable data prefetching in the L2 cache controller, and set
the prefetch offset to 7.

Memcpy performance measured copying 16 MB buffers 78 times:
Data prefetch disabled, prefetch offset 0: 440 MB/s
Enabling data prefetching, prefetch offset 0: 430 MB/s
Enabling data prefetching, prefetch offset 7: 502 MB/s

Overall, this patch gives a 14% improvement in memcpy performance.

Prefetch offset of 8 causes prefetches to cross 4k boundaries
and cannot be used.

Original-author: Gary King <gking@nvidia.com>
Signed-off-by: Chris Fries <C.Fries@motorola.com>
Signed-off-by: Colin Cross <ccross@android.com>
Change-Id: I7ce0810b3f94edc2640df3f643cf81357052f2f1
This commit is contained in:
Chris Fries
2011-02-11 14:26:20 -06:00
committed by Colin Cross
parent 6b53bad8ac
commit 6c77fdda35
1 changed files with 2 additions and 1 deletions
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3
arch/arm/mach-tegra/common.c
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@@ -88,8 +88,9 @@ void __init tegra_init_cache(void)
writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
writel(7, p + L2X0_PREFETCH_OFFSET);
l2x0_init(p, 0x6C480001, 0x8200c3fe);
l2x0_init(p, 0x7C480001, 0x8200c3fe);
#endif
}