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UPSTREAM: ARM: dts: rockchip: add to support emac for rk3036 SoCs

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This patch adds the emac device node for rk3036 SoCs.
We need to let mac clock under the DPLL which is able to provide
the accurate 50MHz what mac_ref need, since that will cause some
unstable things if the cpufreq is working.

Change-Id: Ie6fdbcda7d45cccbc23e1554141cc3c73b554818
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: linux-rockchip@lists.infradead.org
Cc: Xing Zheng <zhengxing@rock-chips.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from git.kernel.org next/linux-next.git master
 commit af671e7bd9)
This commit is contained in:
Xing Zheng
2016-03-14 16:02:00 +08:00
committed by Caesar Wang
parent 0955ef8f83
commit 6cd2a0bdc0
3 changed files with 67 additions and 0 deletions
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14
arch/arm/boot/dts/rk3036-evb.dts
View File

@@ -47,6 +47,20 @@
compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
phy = <&phy0>;
phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* PHY_RST */
phy-reset-duration = <10>; /* millisecond */
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&i2c1 {
status = "okay";

14
arch/arm/boot/dts/rk3036-kylin.dts
View File

@@ -112,6 +112,20 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
phy = <&phy0>;
phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* PHY_RST */
phy-reset-duration = <10>; /* millisecond */
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&emmc {
status = "okay";
};

39
arch/arm/boot/dts/rk3036.dtsi
View File

@@ -187,6 +187,27 @@
status = "disabled";
};
emac: ethernet@10200000 {
compatible = "rockchip,rk3036-emac", "snps,arc-emac";
reg = <0x10200000 0x4000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
rockchip,grf = <&grf>;
clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
clock-names = "hclk", "macref", "macclk";
/*
* Fix the emac parent clock is DPLL instead of APLL.
* since that will cause some unstable things if the cpufreq
* is working. (e.g: the accurate 50MHz what mac_ref need)
*/
assigned-clocks = <&cru SCLK_MACPLL>;
assigned-clock-parents = <&cru PLL_DPLL>;
max-speed = <100>;
phy-mode = "rmii";
status = "disabled";
};
sdmmc: dwmmc@10214000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
@@ -572,6 +593,24 @@
};
};
emac {
emac_xfer: emac-xfer {
rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
<2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
<2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
<2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
<2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
<2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
<2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
<2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
};
emac_mdio: emac-mdio {
rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
<2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,