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Merge commit 'c50cc550bfa0dd274edbe30cbe69acf6e4ea3de9'

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* commit 'c50cc550bfa0dd274edbe30cbe69acf6e4ea3de9':
  usb: typec: tcpm: handle nak for discover modes command
  drm/rockchip: vop2: no need to double attach cluster win share_id_prop
  drm/rockchip: vop2: fix some plane may be lost
  drm/rockchip: analogix_dp: init audio in .late_register() of drm_encoder_func
  arm64: dts: rockchip: add rk3576 nvr demo device tree
  arm64: dts: rockchip: rk3576: Use tab indent on system-status-level
  arm64: configs: Add rk3576_nvr.config
  fs: inline_crypt: add parameter check
  media: rockchip: isp: fix cac for multi sensor

Change-Id: I9123e345a5beffa890ddc7b0aacd6e2300207455
This commit is contained in:
Tao Huang
2024-06-17 20:42:53 +08:00
parent 54de46888b c50cc550bf
commit 6d1fb8fb90
10 changed files with 334 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm64/boot/dts/rockchip/Makefile
View File

@@ -256,6 +256,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-industry-evb-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-iotest-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-iotest-v10-edp2dp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-iotest-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nvr-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-tablet-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-test1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-test1-v10-eink.dtb

238
arch/arm64/boot/dts/rockchip/rk3576-nvr-v10.dts Normal file
View File

@@ -0,0 +1,238 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/display/media-bus-format.h>
#include "rk3576.dtsi"
#include "rk3576-cpu-swap.dtsi"
#include "rk3576-evb2.dtsi"
#include "rk3576-evb2-rk628-bt1120-to-hdmi.dtsi"
#include "rk3576-evb2-rk628-hdmi2csi.dtsi"
#include "rk3576-linux.dtsi"
/ {
model = "Rockchip RK3576 EVB2 V10 NVR Board";
compatible = "rockchip,rk3576-nvr-v10", "rockchip,rk3576";
};
&cluster0_opp_table {
/delete-node/ opp-408000000;
/delete-node/ opp-600000000;
/delete-node/ opp-816000000;
/delete-node/ opp-1008000000;
/delete-node/ opp-1200000000;
/delete-node/ opp-1416000000;
/delete-node/ opp-2208000000;
};
&cluster1_opp_table {
/delete-node/ opp-408000000;
/delete-node/ opp-600000000;
/delete-node/ opp-816000000;
/delete-node/ opp-1008000000;
/delete-node/ opp-1200000000;
/delete-node/ opp-1416000000;
/delete-node/ opp-2304000000;
};
&display_subsystem {
/delete-property/ clkcks;
/delete-property/ clocks-names;
};
&dmc {
status = "okay";
center-supply = <&vdd_ddr_s0>;
mem-supply = <&vdd_logic_s0>;
system-status-level = <
/* system status freq level */
SYS_STATUS_NORMAL DMC_FREQ_LEVEL_HIGH
SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH
SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW
SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_VIDEO_SVEP DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH
SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH
SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH
SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH
SYS_STATUS_HDMIRX DMC_FREQ_LEVEL_HIGH
SYS_STATUS_DEEP_SUSPEND DMC_FREQ_LEVEL_HIGH
>;
auto-freq-en = <0>;
};
&dp0_in_vp0 {
status = "okay";
};
&dp0_in_vp1 {
status = "okay";
};
&dp0_in_vp2 {
status = "okay";
};
&hdmi_in_vp0 {
status = "okay";
};
&hdmi_in_vp1 {
status = "okay";
};
&hdmi_in_vp2 {
status = "okay";
};
&npu_opp_table {
/delete-node/ opp-1000000000;
};
&rgb_in_vp1 {
status = "okay";
};
&rgb_in_vp2 {
status = "okay";
};
&route_dp0 {
status = "okay";
connect = <&vp0_out_dp0>;
force-output;
force_timing {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hfront-porch = <24>;
hsync-len = <136>;
hback-porch = <160>;
vfront-porch = <3>;
vsync-len = <6>;
vback-porch = <29>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
&route_hdmi {
status = "okay";
connect = <&vp0_out_hdmi>;
force-output;
force_timing {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hfront-porch = <24>;
hsync-len = <136>;
hback-porch = <160>;
vfront-porch = <3>;
vsync-len = <6>;
vback-porch = <29>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
&route_rgb {
status = "okay";
connect = <&vp1_out_rgb>;
force-bus-format = <MEDIA_BUS_FMT_YUYV8_1X16>;
force-output;
force_timing {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hfront-porch = <24>;
hsync-len = <136>;
hback-porch = <160>;
vfront-porch = <3>;
vsync-len = <6>;
vback-porch = <29>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <0>;
pixelclk-active = <0>;
};
};
&rk628d {
display-timings {
src-timing {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hfront-porch = <24>;
hsync-len = <136>;
hback-porch = <160>;
vfront-porch = <3>;
vsync-len = <6>;
vback-porch = <29>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <0>;
pixelclk-active = <0>;
};
dst-timing {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hfront-porch = <24>;
hsync-len = <136>;
hback-porch = <160>;
vfront-porch = <3>;
vsync-len = <6>;
vback-porch = <29>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
&rkisp_vir0_sditf {
status = "okay";
};
&rkvpss {
status = "okay";
};
&rkvpss_mmu {
status = "okay";
};
&rkvpss_vir0 {
status = "okay";
};
&vp0 {
assigned-clocks = <&cru DCLK_VP0_SRC>;
assigned-clock-parents = <&cru PLL_VPLL>;
};
&vp1 {
assigned-clocks = <&cru DCLK_VP1_SRC>;
assigned-clock-parents = <&cru PLL_VPLL>;
};
&vp2 {
assigned-clocks = <&cru DCLK_VP2_SRC>;
assigned-clock-parents = <&cru PLL_GPLL>;
};

26
arch/arm64/boot/dts/rockchip/rk3576.dtsi
View File

@@ -794,19 +794,19 @@
upthreshold = <40>;
downdifferential = <20>;
system-status-level = <
/*system status freq level*/
SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH
SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW
SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_VIDEO_SVEP DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH
SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH
SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH
SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH
SYS_STATUS_HDMIRX DMC_FREQ_LEVEL_HIGH
SYS_STATUS_DEEP_SUSPEND DMC_FREQ_LEVEL_HIGH
/* system status freq level */
SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH
SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW
SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_VIDEO_SVEP DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH
SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH
SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH
SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH
SYS_STATUS_HDMIRX DMC_FREQ_LEVEL_HIGH
SYS_STATUS_DEEP_SUSPEND DMC_FREQ_LEVEL_HIGH
>;
auto-freq-en = <1>;
status = "disabled";

5
arch/arm64/configs/rk3576_nvr.config Normal file
View File

@@ -0,0 +1,5 @@
CONFIG_DMABUF_PARTIAL=y
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_HZ=100
CONFIG_HZ_100=y
# CONFIG_HZ_250 is not set

54
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
View File

@@ -569,6 +569,35 @@ static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
return 0;
}
static int analogix_dp_encoder_late_register(struct drm_encoder *encoder)
{
struct rockchip_dp_device *dp = encoder_to_dp(encoder);
struct device *dev = dp->dev;
if (dp->data->audio) {
struct hdmi_codec_pdata codec_data = {
.ops = &rockchip_dp_audio_codec_ops,
.spdif = 1,
.i2s = 1,
.max_i2s_channels = 8,
};
dp->audio_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
PLATFORM_DEVID_AUTO,
&codec_data,
sizeof(codec_data));
if (IS_ERR(dp->audio_pdev))
dev_warn(dev, "failed to initialize audio\n");
}
return 0;
}
static const struct drm_encoder_funcs analogix_dp_encoder_func = {
.destroy = drm_encoder_cleanup,
.late_register = analogix_dp_encoder_late_register,
};
static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
{
struct drm_encoder *encoder = &dp->encoder.encoder;
@@ -580,8 +609,8 @@ static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
dev->of_node);
DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
ret = drm_simple_encoder_init(drm_dev, encoder,
DRM_MODE_ENCODER_TMDS);
ret = drm_encoder_init(drm_dev, encoder, &analogix_dp_encoder_func,
DRM_MODE_ENCODER_TMDS, NULL);
if (ret) {
DRM_ERROR("failed to initialize encoder with drm\n");
return ret;
@@ -611,25 +640,6 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
dp->plat_data.encoder = &dp->encoder.encoder;
}
if (dp->data->audio) {
struct hdmi_codec_pdata codec_data = {
.ops = &rockchip_dp_audio_codec_ops,
.spdif = 1,
.i2s = 1,
.max_i2s_channels = 8,
};
dp->audio_pdev =
platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
PLATFORM_DEVID_AUTO,
&codec_data,
sizeof(codec_data));
if (IS_ERR(dp->audio_pdev)) {
ret = PTR_ERR(dp->audio_pdev);
goto err_cleanup_encoder;
}
}
ret = analogix_dp_bind(dp->adp, drm_dev);
if (ret)
goto err_unregister_audio_pdev;
@@ -639,8 +649,6 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
err_unregister_audio_pdev:
if (dp->audio_pdev)
platform_device_unregister(dp->audio_pdev);
err_cleanup_encoder:
dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
return ret;
}

7
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -12738,9 +12738,6 @@ static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win, unsigned lon
drm_object_attach_property(&win->base.base, private->async_commit_prop, 0);
if (win->feature & (WIN_FEATURE_CLUSTER_SUB | WIN_FEATURE_CLUSTER_MAIN))
drm_object_attach_property(&win->base.base, private->share_id_prop, win->plane_id);
if (win->parent)
drm_object_attach_property(&win->base.base, private->share_id_prop,
win->parent->base.base.id);
@@ -13157,8 +13154,10 @@ static int vop2_create_crtc(struct vop2 *vop2, uint8_t enabled_vp_mask)
/*
* make sure that the vp to be registered has at least one connector.
*/
if (!(enabled_vp_mask & BIT(vp->id)))
if (!(enabled_vp_mask & BIT(vp->id))) {
vop2->vps[vp->id].primary_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID;
continue;
}
/*
* we assume a vp with a zero plane_mask(set from dts or bootloader)

5
drivers/media/platform/rockchip/isp/hw.c
View File

@@ -573,6 +573,11 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
writel(val, base + ISP_MPFBC_HEAD_PTR);
val = rkisp_read_reg_cache(isp, MI_SWS_3A_WR_BASE);
writel(val, base + MI_SWS_3A_WR_BASE);
/* force for cac to read lut */
if (dev->isp_ver >= ISP_V33) {
val = rkisp_read_reg_cache(isp, ISP3X_CAC_BASE);
writel(val, base + ISP3X_CAC_BASE);
}
}
if (dev->is_single) {

32
drivers/media/platform/rockchip/isp/rkisp.c
View File

@@ -675,9 +675,21 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
writel(0, hw->base_addr + CIF_IRCL);
}
/* sensor mode & index */
if (dev->isp_ver >= ISP_V21) {
val = rkisp_read_reg_cache(dev, ISP_ACQ_H_OFFS);
val |= ISP21_SENSOR_INDEX(dev->multi_index);
if (dev->isp_ver == ISP_V32_L)
val |= ISP32L_SENSOR_MODE(dev->multi_mode);
else
val |= ISP21_SENSOR_MODE(dev->multi_mode);
writel(val, hw->base_addr + ISP_ACQ_H_OFFS);
if (hw->unite == ISP_UNITE_TWO)
writel(val, hw->base_next_addr + ISP_ACQ_H_OFFS);
}
rkisp_update_regs(dev, CTRL_VI_ISP_PATH, SUPER_IMP_COLOR_CR);
rkisp_update_regs(dev, DUAL_CROP_M_H_OFFS, ISP3X_DUAL_CROP_FBC_V_SIZE);
rkisp_update_regs(dev, ISP_ACQ_H_OFFS, DUAL_CROP_CTRL);
rkisp_update_regs(dev, ISP_ACQ_V_OFFS, DUAL_CROP_CTRL);
rkisp_update_regs(dev, ISP39_LDCV_BIC_TABLE0, MI_WR_CTRL);
rkisp_update_regs(dev, SELF_RESIZE_SCALE_HY, ISP39_LDCV_CTRL);
rkisp_update_regs(dev, ISP32_BP_RESIZE_SCALE_HY, SELF_RESIZE_CTRL);
@@ -702,21 +714,9 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
rkisp_write(dev, ISP39_MAIN_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true);
}
/* sensor mode & index */
if (dev->isp_ver >= ISP_V21) {
val = rkisp_read_reg_cache(dev, ISP_ACQ_H_OFFS);
val |= ISP21_SENSOR_INDEX(dev->multi_index);
if (dev->isp_ver == ISP_V32_L || dev->isp_ver == ISP_V39)
val |= ISP32L_SENSOR_MODE(dev->multi_mode);
else
val |= ISP21_SENSOR_MODE(dev->multi_mode);
writel(val, hw->base_addr + ISP_ACQ_H_OFFS);
if (hw->unite == ISP_UNITE_TWO)
writel(val, hw->base_next_addr + ISP_ACQ_H_OFFS);
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"sensor mode:%d index:%d | 0x%x\n",
dev->multi_mode, dev->multi_index, val);
}
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"sensor mode:%d index:%d | 0x%x\n",
dev->multi_mode, dev->multi_index, rkisp_read(dev, ISP_ACQ_H_OFFS, true));
is_upd = true;
}

20
drivers/usb/typec/tcpm/tcpm.c
View File

@@ -1807,7 +1807,27 @@ static int tcpm_pd_svdm(struct tcpm_port *port, struct typec_altmode *adev,
}
fallthrough;
case CMD_DISCOVER_SVID:
break;
case CMD_DISCOVER_MODES:
/*
* 6.4.4.3.3
* A Responder that does not support any Modes Shall return a NAK.
*
* When Initiator meets this case, it should skip
* consuming modes and continue to request Discover
* Modes for the rest of SVIDs or register altmodes
* that have been consumed in previous ACK.
*/
modep->svid_index++;
if (modep->svid_index < modep->nsvids) {
u16 svid = modep->svids[modep->svid_index];
response[0] = VDO(svid, 1, svdm_version, CMD_DISCOVER_MODES);
rlen = 1;
} else if (port->data_role == TYPEC_HOST) {
tcpm_register_partner_altmodes(port);
}
break;
case VDO_CMD_VENDOR(0) ... VDO_CMD_VENDOR(15):
break;
case CMD_ENTER_MODE:

2
fs/crypto/inline_crypt.c
View File

@@ -263,6 +263,8 @@ int fscrypt_derive_sw_secret(struct super_block *sb,
bool __fscrypt_inode_uses_inline_crypto(const struct inode *inode)
{
if (!inode->i_crypt_info)
return false;
return inode->i_crypt_info->ci_inlinecrypt;
}
EXPORT_SYMBOL_GPL(__fscrypt_inode_uses_inline_crypto);