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drm/bridge: analogix_dp: Move PLL lock check to analogix_dp_set_link_bandwidth()

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Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I7c094f84d7aeb2a9e8b8343c634bb8a01ab8e5dd
This commit is contained in:
Wyon Bi
2020-11-09 20:45:49 +08:00
committed by Tao Huang
parent d9e410b03c
commit 6d45fa9b4d
2 changed files with 12 additions and 36 deletions
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23
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
View File

@@ -237,7 +237,7 @@ static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
static int analogix_dp_link_start(struct analogix_dp_device *dp)
{
u8 buf[4];
int lane, lane_count, pll_tries, retval;
int lane, lane_count, retval;
lane_count = dp->link_train.lane_count;
@@ -271,18 +271,6 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
DP_TRAIN_PRE_EMPH_LEVEL_0;
analogix_dp_set_lane_link_training(dp);
/* Wait for PLL lock */
pll_tries = 0;
while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
dev_err(dp->dev, "Wait for PLL lock timed out\n");
return -ETIMEDOUT;
}
pll_tries++;
usleep_range(90, 120);
}
/* Set training pattern 1 */
analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
@@ -642,7 +630,6 @@ static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
{
int ret;
u8 link_align, link_status[2];
enum pll_status status;
analogix_dp_reset_macro(dp);
@@ -650,14 +637,6 @@ static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
analogix_dp_set_lane_link_training(dp);
ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
status != PLL_UNLOCKED, 120,
120 * DP_TIMEOUT_LOOP_COUNT);
if (ret) {
DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
return ret;
}
/* source Set training pattern 1 */
analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
/* From DP spec, pattern must be on-screen for a minimum 500us */

25
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
View File

@@ -374,7 +374,6 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
int analogix_dp_init_analog_func(struct analogix_dp_device *dp)
{
u32 reg;
int timeout_loop = 0;
analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
@@ -386,18 +385,7 @@ int analogix_dp_init_analog_func(struct analogix_dp_device *dp)
analogix_dp_write(dp, ANALOGIX_DP_DEBUG_CTL, reg);
/* Power up PLL */
if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
analogix_dp_set_pll_power_down(dp, 0);
while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
timeout_loop++;
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "failed to get pll lock status\n");
return -ETIMEDOUT;
}
usleep_range(10, 20);
}
}
analogix_dp_set_pll_power_down(dp, 0);
/* Enable Serdes FIFO function and Link symbol clock domain module */
reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2);
@@ -544,11 +532,20 @@ void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
{
u32 reg;
u32 reg, status;
int ret;
reg = bwtype;
if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62))
analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, reg);
ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
status != PLL_UNLOCKED, 120,
120 * DP_TIMEOUT_LOOP_COUNT);
if (ret) {
dev_err(dp->dev, "Wait for pll lock failed %d\n", ret);
return;
}
}
void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)