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vdin: fix black screen caused by vdin_check_vs

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PD#160716: vdin: fix black screen caused by vdin_check_vs

1.add vdin msrclk in dts
2.remove vdin_check_vf

Change-Id: Ie0a63821f2eea85cf8f67202b067e4f2b491066c
Signed-off-by: Bencheng Jing <bencheng.jing@amlogic.com>
This commit is contained in:
Bencheng Jing
2018-02-09 22:55:08 +08:00
committed by Yixun Lan
parent e4341e80c1
commit 6d796b43ec
7 changed files with 18 additions and 84 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm64/boot/dts/amlogic/txlx_t962e_r321.dts
View File

@@ -483,9 +483,9 @@
cma_size = <190>;
interrupts = <0 83 1>;
rdma-irq = <2>;
//clocks = <&clock CLK_FPLL_DIV5>,
// <&clock CLK_VDIN_MEAS_CLK>;
//clock-names = "fclk_div5", "cts_vdin_meas_clk";
clocks = <&clkc CLKID_FCLK_DIV5>,
<&clkc CLKID_VDIN_MEAS_COMP>;
clock-names = "fclk_div5", "cts_vdin_meas_clk";
vdin_id = <0>;
/* vdin write mem color depth support:
* bit0:support 8bit
@@ -506,9 +506,9 @@
flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/
interrupts = <0 85 1>;
rdma-irq = <4>;
//clocks = <&clock CLK_FPLL_DIV5>,
// <&clock CLK_VDIN_MEAS_CLK>;
//clock-names = "fclk_div5", "cts_vdin_meas_clk";
clocks = <&clkc CLKID_FCLK_DIV5>,
<&clkc CLKID_VDIN_MEAS_COMP>;
clock-names = "fclk_div5", "cts_vdin_meas_clk";
vdin_id = <1>;
/* vdin write mem color depth support:
* bit0:support 8bit

12
arch/arm64/boot/dts/amlogic/txlx_t962x_r311_1g.dts
View File

@@ -484,9 +484,9 @@
cma_size = <190>;
interrupts = <0 83 1>;
rdma-irq = <2>;
//clocks = <&clock CLK_FPLL_DIV5>,
// <&clock CLK_VDIN_MEAS_CLK>;
//clock-names = "fclk_div5", "cts_vdin_meas_clk";
clocks = <&clkc CLKID_FCLK_DIV5>,
<&clkc CLKID_VDIN_MEAS_COMP>;
clock-names = "fclk_div5", "cts_vdin_meas_clk";
vdin_id = <0>;
/* vdin write mem color depth support:
* bit0:support 8bit
@@ -507,9 +507,9 @@
flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/
interrupts = <0 85 1>;
rdma-irq = <4>;
//clocks = <&clock CLK_FPLL_DIV5>,
// <&clock CLK_VDIN_MEAS_CLK>;
//clock-names = "fclk_div5", "cts_vdin_meas_clk";
clocks = <&clkc CLKID_FCLK_DIV5>,
<&clkc CLKID_VDIN_MEAS_COMP>;
clock-names = "fclk_div5", "cts_vdin_meas_clk";
vdin_id = <1>;
/* vdin write mem color depth support:
* bit0:support 8bit

12
arch/arm64/boot/dts/amlogic/txlx_t962x_r311_2g.dts
View File

@@ -484,9 +484,9 @@
cma_size = <190>;
interrupts = <0 83 1>;
rdma-irq = <2>;
//clocks = <&clock CLK_FPLL_DIV5>,
// <&clock CLK_VDIN_MEAS_CLK>;
//clock-names = "fclk_div5", "cts_vdin_meas_clk";
clocks = <&clkc CLKID_FCLK_DIV5>,
<&clkc CLKID_VDIN_MEAS_COMP>;
clock-names = "fclk_div5", "cts_vdin_meas_clk";
vdin_id = <0>;
/* vdin write mem color depth support:
* bit0:support 8bit
@@ -507,9 +507,9 @@
flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/
interrupts = <0 85 1>;
rdma-irq = <4>;
//clocks = <&clock CLK_FPLL_DIV5>,
// <&clock CLK_VDIN_MEAS_CLK>;
//clock-names = "fclk_div5", "cts_vdin_meas_clk";
clocks = <&clkc CLKID_FCLK_DIV5>,
<&clkc CLKID_VDIN_MEAS_COMP>;
clock-names = "fclk_div5", "cts_vdin_meas_clk";
vdin_id = <1>;
/* vdin write mem color depth support:
* bit0:support 8bit

44
drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c
View File

@@ -145,16 +145,6 @@ static unsigned int vpu_reg_27af = 0x3;
#define VDIN_PIXELCLK_4K_30HZ 248832000
#define VDIN_PIXELCLK_4K_60HZ 497664000
/* check hcnt/vcnt after N*vs. */
#define VDIN_WAIT_VALID_VS 2
/* ignore n*vs which have wrong data. */
#define VDIN_IGNORE_VS_CNT 20
/* the diff value between normal/bad data */
#define VDIN_MEAS_HSCNT_DIFF 0x50
/* the diff value between normal/bad data */
#define VDIN_MEAS_VSCNT_DIFF 0x50
#if 0/*ndef VDIN_DEBUG*/
#undef pr_info
#define pr_info(fmt, ...)
@@ -2743,40 +2733,6 @@ bool vdin_write_done_check(unsigned int offset, struct vdin_dev_s *devp)
}
#endif
/* check invalid vs to avoid screen flicker */
bool vdin_check_vs(struct vdin_dev_s *devp)
{
bool ret = false;
unsigned int dh = 0, dv = 0;
/* check vs after n*vs avoid unstable signal after TVIN_IOC_START_DEC*/
if (devp->vs_cnt_valid++ >= VDIN_WAIT_VALID_VS)
devp->vs_cnt_valid = VDIN_WAIT_VALID_VS;
/* check hcnt64/cycle to find format changed */
if (devp->hcnt64 < devp->hcnt64_tag)
dh = devp->hcnt64_tag - devp->hcnt64;
else
dh = devp->hcnt64 - devp->hcnt64_tag;
if (devp->cycle < devp->cycle_tag)
dv = devp->cycle_tag - devp->cycle;
else
dv = devp->cycle - devp->cycle_tag;
if ((dh > VDIN_MEAS_HSCNT_DIFF) || (dv > VDIN_MEAS_VSCNT_DIFF)) {
devp->hcnt64_tag = devp->hcnt64;
devp->cycle_tag = devp->cycle;
if (devp->vs_cnt_valid >= VDIN_WAIT_VALID_VS)
devp->vs_cnt_ignore = VDIN_IGNORE_VS_CNT;
}
/* Do not send data of format changed to video buffer */
if (devp->vs_cnt_ignore) {
devp->vs_cnt_ignore--;
ret = true;
}
return ret;
}
/*
cycle = delta_stamp = ((1/fps)/(1/msr_clk))*(vsync_span+1)
msr_clk/fps unit is HZ

1
drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.h
View File

@@ -150,7 +150,6 @@ extern void vdin_set_matrixs(struct vdin_dev_s *devp, unsigned char no,
extern bool vdin_check_cycle(struct vdin_dev_s *devp);
extern bool vdin_write_done_check(unsigned int offset,
struct vdin_dev_s *devp);
extern bool vdin_check_vs(struct vdin_dev_s *devp);
extern void vdin_calculate_duration(struct vdin_dev_s *devp);
extern void vdin_wr_reverse(unsigned int offset, bool hreverse,
bool vreverse);

16
drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c
View File

@@ -499,11 +499,7 @@ void vdin_start_dec(struct vdin_dev_s *devp)
/* devp->stamp_valid = false; */
devp->stamp = 0;
devp->cycle = 0;
devp->cycle_tag = 0;
devp->hcnt64 = 0;
devp->hcnt64_tag = 0;
devp->vs_cnt_valid = 0;
devp->vs_cnt_ignore = 0;
memset(&devp->parm.histgram[0], 0, sizeof(unsigned short) * 64);
@@ -1253,16 +1249,6 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
devp->hcnt64 = vdin_get_meas_hcnt64(offset);
/* ignore invalid vs base on the continuous fields
* different cnt to void screen flicker
*/
if (vdin_check_vs(devp) &&
(!(isr_flag & VDIN_BYPASS_VSYNC_CHECK))
&& (!(devp->flags & VDIN_FLAG_SNOW_FLAG))) {
devp->vdin_irq_flag = 5;
vdin_drop_cnt++;
goto irq_handled;
}
sm_ops = devp->frontend->sm_ops;
last_field_type = devp->curr_field_type;
@@ -2435,7 +2421,6 @@ static int vdin_drv_probe(struct platform_device *pdev)
} else {
clk_set_parent(vdevp->msr_clk, clk);
vdevp->msr_clk_val = clk_get_rate(vdevp->msr_clk);
clk_put(vdevp->msr_clk);
pr_info("%s: vdin msr clock is %d MHZ\n", __func__,
vdevp->msr_clk_val/1000000);
}
@@ -2462,7 +2447,6 @@ static int vdin_drv_probe(struct platform_device *pdev)
if (!IS_ERR(vdevp->msr_clk)) {
vdevp->msr_clk_val =
clk_get_rate(vdevp->msr_clk);
clk_put(vdevp->msr_clk);
pr_info("%s: vdin[%d] clock is %d MHZ\n",
__func__, vdevp->index,
vdevp->msr_clk_val/1000000);

5
drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h
View File

@@ -82,7 +82,6 @@
/*values of vdin isr bypass check flag */
#define VDIN_BYPASS_STOP_CHECK 0x00000001
#define VDIN_BYPASS_CYC_CHECK 0x00000002
#define VDIN_BYPASS_VSYNC_CHECK 0x00000004
#define VDIN_BYPASS_VGA_CHECK 0x00000008
#define VDIN_CANVAS_MAX_CNT 9
@@ -218,16 +217,12 @@ struct vdin_dev_s {
char irq_name[12];
/* address offset(vdin0/vdin1/...) */
unsigned int addr_offset;
unsigned int vs_cnt_valid;
unsigned int vs_cnt_ignore;
unsigned int unstable_flag;
unsigned int abnormal_cnt;
unsigned int stamp;
unsigned int hcnt64;
unsigned int cycle;
unsigned int hcnt64_tag;
unsigned int cycle_tag;
unsigned int start_time;/* ms vdin start time */
int rdma_handle;