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media: rockchip: hdmirx: add debug node
Signed-off-by: Chen Shunqing <csq@rock-chips.com> Change-Id: I5ab694ae4ec5c7a5a991ef3373781670ab5dcd20
This commit is contained in:
Chen Shunqing
@@ -6,8 +6,10 @@
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*/
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/fs.h>
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#include <linux/gpio/consumer.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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@@ -23,6 +25,7 @@
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/rockchip/rockchip_sip.h>
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#include <linux/seq_file.h>
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#include <linux/v4l2-dv-timings.h>
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#include <linux/workqueue.h>
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#include <media/cec.h>
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@@ -107,6 +110,19 @@ enum ddr_store_fmt {
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STORE_YUV422_16BIT = 9,
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};
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enum hdmirx_reg_attr {
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HDMIRX_ATTR_RW = 0,
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HDMIRX_ATTR_RO = 1,
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HDMIRX_ATTR_WO = 2,
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HDMIRX_ATTR_RE = 3,
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};
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struct hdmirx_reg_table {
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int reg_base;
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int reg_end;
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enum hdmirx_reg_attr attr;
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};
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struct hdmirx_buffer {
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struct vb2_v4l2_buffer vb;
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struct list_head queue;
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@@ -188,6 +204,7 @@ struct rk_hdmirx_dev {
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struct hdmirx_cec *cec;
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struct cec_notifier *cec_notifier;
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spinlock_t dma_rst_lock;
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struct dentry *debugfs_dir;
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};
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static bool tx_5v_power_present(struct rk_hdmirx_dev *hdmirx_dev);
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@@ -917,6 +934,40 @@ static int wait_reg_bit_status(struct rk_hdmirx_dev *hdmirx_dev,
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return 0;
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}
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static int hdmirx_phy_register_read(struct rk_hdmirx_dev *hdmirx_dev,
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u32 phy_reg, u32 *val)
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{
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u32 i;
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struct device *dev = hdmirx_dev->dev;
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hdmirx_dev->cr_read_done = false;
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/* clear irq status */
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hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
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/* en irq */
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hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N,
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PHYCREG_CR_READ_DONE, PHYCREG_CR_READ_DONE);
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/* write phy reg addr */
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hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG1, phy_reg);
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/* config read enable */
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hdmirx_writel(hdmirx_dev, PHYCREG_CONTROL, PHYCREG_CR_PARA_READ_P);
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for (i = 0; i < 50; i++) {
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usleep_range(200, 210);
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if (hdmirx_dev->cr_read_done)
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break;
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}
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if (i == 50) {
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dev_err(dev, "%s wait cr read done failed!\n", __func__);
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return -1;
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}
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/* read phy reg val */
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*val = hdmirx_readl(hdmirx_dev, PHYCREG_STATUS);
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return 0;
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}
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static int hdmirx_phy_register_write(struct rk_hdmirx_dev *hdmirx_dev,
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u32 phy_reg, u32 val)
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{
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@@ -2823,6 +2874,358 @@ static struct attribute *hdmirx_attrs[] = {
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};
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ATTRIBUTE_GROUPS(hdmirx);
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static const struct hdmirx_reg_table hdmirx_ctrl_table[] = {
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{0x00, 0x0c, HDMIRX_ATTR_RO},
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{0x10, 0x10, HDMIRX_ATTR_RE},
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{0x14, 0x1c, HDMIRX_ATTR_RO},
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{0x20, 0x20, HDMIRX_ATTR_WO},
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{0x24, 0x28, HDMIRX_ATTR_RW},
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{0x40, 0x40, HDMIRX_ATTR_WO},
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{0x44, 0x48, HDMIRX_ATTR_RW},
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{0x50, 0x50, HDMIRX_ATTR_RW},
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{0x60, 0x60, HDMIRX_ATTR_RW},
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{0x64, 0x6c, HDMIRX_ATTR_RE},
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{0x70, 0x70, HDMIRX_ATTR_RE},
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{0x74, 0x74, HDMIRX_ATTR_RW},
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{0x78, 0x78, HDMIRX_ATTR_RE},
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{0x7c, 0x7c, HDMIRX_ATTR_RO},
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{0x80, 0x84, HDMIRX_ATTR_RO},
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{0xc0, 0xc0, HDMIRX_ATTR_RO},
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{0xc4, 0xc4, HDMIRX_ATTR_RE},
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{0xc8, 0xd8, HDMIRX_ATTR_RW},
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{0xe0, 0xe8, HDMIRX_ATTR_RW},
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{0xec, 0xf0, HDMIRX_ATTR_WO},
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{0xf4, 0xf8, HDMIRX_ATTR_RW},
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{0x150, 0x150, HDMIRX_ATTR_RO},
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{0x160, 0x164, HDMIRX_ATTR_RW},
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{0x210, 0x218, HDMIRX_ATTR_RW},
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{0x220, 0x228, HDMIRX_ATTR_RE},
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{0x22c, 0x22c, HDMIRX_ATTR_RW},
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{0x230, 0x230, HDMIRX_ATTR_WO},
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{0x234, 0x234, HDMIRX_ATTR_RO},
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{0x270, 0x274, HDMIRX_ATTR_RO},
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{0x278, 0x278, HDMIRX_ATTR_WO},
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{0x27c, 0x27c, HDMIRX_ATTR_RO},
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{0x290, 0x294, HDMIRX_ATTR_RW},
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{0x2a0, 0x2a8, HDMIRX_ATTR_WO},
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{0x2ac, 0x2ac, HDMIRX_ATTR_RO},
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{0x2b0, 0x2b4, HDMIRX_ATTR_RE},
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{0x2b8, 0x2d8, HDMIRX_ATTR_RW},
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{0x2e0, 0x2e4, HDMIRX_ATTR_RW},
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{0x2f0, 0x304, HDMIRX_ATTR_RW},
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/* {0x3f0, 0x410, HDMIRX_ATTR_WO}, */
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{0x420, 0x434, HDMIRX_ATTR_RW},
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{0x460, 0x460, HDMIRX_ATTR_RW},
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/* {0x464, 0x478, HDMIRX_ATTR_WO}, */
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{0x480, 0x494, HDMIRX_ATTR_RW},
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{0x580, 0x580, HDMIRX_ATTR_RW},
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{0x584, 0x584, HDMIRX_ATTR_WO},
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{0x588, 0x59c, HDMIRX_ATTR_RO},
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{0x5a0, 0x5a4, HDMIRX_ATTR_RE},
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{0x5a8, 0x5e0, HDMIRX_ATTR_RW},
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{0x700, 0x728, HDMIRX_ATTR_RW},
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{0x740, 0x74c, HDMIRX_ATTR_RW},
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{0x760, 0x768, HDMIRX_ATTR_RW},
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{0x7c0, 0x7c0, HDMIRX_ATTR_RE},
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{0x7c4, 0x7d4, HDMIRX_ATTR_RW},
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{0x1580, 0x1598, HDMIRX_ATTR_RO},
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{0x2000, 0x2000, HDMIRX_ATTR_WO},
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{0x2004, 0x200c, HDMIRX_ATTR_RW},
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{0x2020, 0x2030, HDMIRX_ATTR_RW},
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{0x2040, 0x2050, HDMIRX_ATTR_RO},
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{0x2060, 0x2068, HDMIRX_ATTR_RW},
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{0x4400, 0x442c, HDMIRX_ATTR_RW},
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{0x4430, 0x446c, HDMIRX_ATTR_RO},
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{0x5000, 0x5000, HDMIRX_ATTR_RO},
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{0x5010, 0x5014, HDMIRX_ATTR_RW},
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{0x5020, 0x5024, HDMIRX_ATTR_RW},
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{0x5030, 0x5034, HDMIRX_ATTR_RW},
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{0x5040, 0x5044, HDMIRX_ATTR_RW},
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{0x5050, 0x5054, HDMIRX_ATTR_RW},
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{0x5080, 0x5084, HDMIRX_ATTR_RW},
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{0x5090, 0x5094, HDMIRX_ATTR_RW},
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{0x50a0, 0x50a4, HDMIRX_ATTR_RW},
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{0x50c0, 0x50c4, HDMIRX_ATTR_RW},
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{0x50d0, 0x50d4, HDMIRX_ATTR_RW},
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{0x50e0, 0x50e4, HDMIRX_ATTR_RW},
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{0x5100, 0x5104, HDMIRX_ATTR_RW},
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};
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static int hdmirx_ctrl_show(struct seq_file *s, void *v)
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{
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struct rk_hdmirx_dev *hdmirx_dev = s->private;
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u32 i = 0, j = 0, val = 0;
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seq_puts(s, "\n--------------------hdmirx ctrl--------------------");
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for (i = 0; i < ARRAY_SIZE(hdmirx_ctrl_table); i++) {
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for (j = hdmirx_ctrl_table[i].reg_base;
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j <= hdmirx_ctrl_table[i].reg_end; j += 4) {
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if (j % 16 == 0)
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seq_printf(s, "\n%08x:", j);
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if (hdmirx_ctrl_table[i].attr == HDMIRX_ATTR_WO)
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seq_puts(s, " WO......");
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else if (hdmirx_ctrl_table[i].attr == HDMIRX_ATTR_RE)
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seq_puts(s, " Reserved");
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else {
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val = hdmirx_readl(hdmirx_dev, j);
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seq_printf(s, " %08x", val);
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}
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}
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}
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seq_puts(s, "\n---------------------------------------------------\n");
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return 0;
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}
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static int hdmirx_ctrl_open(struct inode *inode, struct file *file)
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{
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return single_open(file, hdmirx_ctrl_show, inode->i_private);
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}
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static ssize_t
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hdmirx_ctrl_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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{
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struct rk_hdmirx_dev *hdmirx_dev =
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((struct seq_file *)file->private_data)->private;
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u32 reg, val;
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char kbuf[25];
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if (copy_from_user(kbuf, buf, count))
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return -EFAULT;
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if (sscanf(kbuf, "%x%x", ®, &val) == -1)
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return -EFAULT;
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if (reg > CEC_INT_CLEAR) {
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dev_err(hdmirx_dev->dev, "it is no a hdmirx register\n");
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return count;
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}
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dev_info(hdmirx_dev->dev, "/**********hdmi register config******/");
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dev_info(hdmirx_dev->dev, "\n reg=%x val=%x\n", reg, val);
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hdmirx_writel(hdmirx_dev, reg, val);
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return count;
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}
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static const struct file_operations hdmirx_ctrl_fops = {
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.owner = THIS_MODULE,
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.open = hdmirx_ctrl_open,
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.read = seq_read,
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.write = hdmirx_ctrl_write,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int hdmirx_phy_show(struct seq_file *s, void *v)
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{
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struct rk_hdmirx_dev *hdmirx_dev = s->private;
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u32 i = 0, val = 0;
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seq_puts(s, "\n--------------------hdmirx phy---------------------\n");
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hdmirx_phy_register_read(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, &val);
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seq_printf(s, "%08x: %08x\n", SUP_DIG_ANA_CREGS_SUP_ANA_NC, val);
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for (i = LANE0_DIG_ASIC_RX_OVRD_OUT_0;
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i <= LANE3_DIG_ASIC_RX_OVRD_OUT_0; i += 0x100) {
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hdmirx_phy_register_read(hdmirx_dev, i, &val);
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seq_printf(s, "%08x: %08x\n", i, val);
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}
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for (i = LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2;
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i <= LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2; i += 0x100) {
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hdmirx_phy_register_read(hdmirx_dev, i, &val);
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seq_printf(s, "%08x: %08x\n", i, val);
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}
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hdmirx_phy_register_read(hdmirx_dev,
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HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_FSM_CONFIG, &val);
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seq_printf(s, "%08x: %08x\n",
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HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_FSM_CONFIG, val);
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hdmirx_phy_register_read(hdmirx_dev,
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HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_ADAPT_REF_FOM, &val);
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seq_printf(s, "%08x: %08x\n",
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HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_ADAPT_REF_FOM, val);
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for (i = RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT;
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i <= RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT; i += 0x100) {
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hdmirx_phy_register_read(hdmirx_dev, i, &val);
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seq_printf(s, "%08x: %08x\n", i, val);
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}
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for (i = RAWLANE0_DIG_AON_FAST_FLAGS;
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i <= RAWLANE3_DIG_AON_FAST_FLAGS; i += 0x100) {
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hdmirx_phy_register_read(hdmirx_dev, i, &val);
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seq_printf(s, "%08x: %08x\n", i, val);
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}
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seq_puts(s, "---------------------------------------------------\n");
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return 0;
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}
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static int hdmirx_phy_open(struct inode *inode, struct file *file)
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{
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return single_open(file, hdmirx_phy_show, inode->i_private);
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}
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static ssize_t
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hdmirx_phy_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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{
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struct rk_hdmirx_dev *hdmirx_dev =
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((struct seq_file *)file->private_data)->private;
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u32 reg, val;
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char kbuf[25];
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if (copy_from_user(kbuf, buf, count))
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return -EFAULT;
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if (sscanf(kbuf, "%x%x", ®, &val) == -1)
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return -EFAULT;
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if (reg > RAWLANE3_DIG_AON_FAST_FLAGS) {
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dev_err(hdmirx_dev->dev, "it is no a hdmirx register\n");
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return count;
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}
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dev_info(hdmirx_dev->dev, "/**********hdmi register config******/");
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dev_info(hdmirx_dev->dev, "\n reg=%x val=%x\n", reg, val);
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hdmirx_phy_register_write(hdmirx_dev, reg, val);
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return count;
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}
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static const struct file_operations hdmirx_phy_fops = {
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.owner = THIS_MODULE,
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.open = hdmirx_phy_open,
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.read = seq_read,
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.write = hdmirx_phy_write,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int hdmirx_status_show(struct seq_file *s, void *v)
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{
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struct rk_hdmirx_dev *hdmirx_dev = s->private;
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struct v4l2_dv_timings timings = hdmirx_dev->timings;
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struct v4l2_bt_timings *bt = &timings.bt;
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bool plugin;
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u32 htot, vtot, fps;
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u32 val;
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plugin = tx_5v_power_present(hdmirx_dev);
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seq_printf(s, "status: %s\n", plugin ? "plugin" : "plugout");
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if (!plugin)
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return 0;
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val = hdmirx_readl(hdmirx_dev, SCDC_REGBANK_STATUS3);
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seq_puts(s, "Clk-Ch:");
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if (val & 0x1)
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seq_puts(s, "Lock\t");
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else
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seq_puts(s, "Unlock\t");
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seq_puts(s, "Ch0:");
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if (val & 0x2)
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seq_puts(s, "Lock\t");
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else
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seq_puts(s, "Unlock\t");
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seq_puts(s, "Ch1:");
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if (val & 0x4)
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seq_puts(s, "Lock\t");
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else
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seq_puts(s, "Unlock\t");
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seq_puts(s, "Ch2:");
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if (val & 0x8)
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seq_puts(s, "Lock\n");
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else
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seq_puts(s, "Unlock\n");
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val = hdmirx_readl(hdmirx_dev, 0x598);
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if (val & 0x8000)
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seq_printf(s, "Ch0-Err:%d\t", (val & 0x7fff));
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if (val & 0x80000000)
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seq_printf(s, "Ch1-Err:%d\t", (val & 0x7fff0000) >> 16);
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val = hdmirx_readl(hdmirx_dev, 0x59c);
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if (val & 0x8000)
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seq_printf(s, "Ch2-Err:%d", (val & 0x7fff));
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seq_puts(s, "\n");
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htot = bt->width + bt->hfrontporch + bt->hsync + bt->hbackporch;
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vtot = bt->height + bt->vfrontporch + bt->vsync + bt->vbackporch;
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if (bt->interlaced)
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vtot /= 2;
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fps = (bt->pixelclock + (htot * vtot) / 2) / (htot * vtot);
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if (hdmirx_dev->pix_fmt == HDMIRX_YUV420)
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fps *= 2;
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seq_puts(s, "Color Format: ");
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if (hdmirx_dev->pix_fmt == HDMIRX_RGB888)
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seq_puts(s, "RGB");
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else if (hdmirx_dev->pix_fmt == HDMIRX_YUV422)
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seq_puts(s, "YUV422");
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else if (hdmirx_dev->pix_fmt == HDMIRX_YUV444)
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seq_puts(s, "YUV444");
|
||||
else if (hdmirx_dev->pix_fmt == HDMIRX_YUV420)
|
||||
seq_puts(s, "YUV420");
|
||||
else
|
||||
seq_puts(s, "UNKNOWN");
|
||||
|
||||
val = hdmirx_readl(hdmirx_dev, DMA_CONFIG1) & DDR_STORE_FORMAT_MASK;
|
||||
val = val >> 12;
|
||||
seq_puts(s, "\t\t\tStore Format: ");
|
||||
if (val == STORE_RGB888)
|
||||
seq_puts(s, "RGB\n");
|
||||
else if (val == STORE_RGBA_ARGB)
|
||||
seq_puts(s, "RGBA/ARGB\n");
|
||||
else if (val == STORE_YUV420_8BIT)
|
||||
seq_puts(s, "YUV420 (8 bit)\n");
|
||||
else if (val == STORE_YUV420_10BIT)
|
||||
seq_puts(s, "YUV420 (10 bit)\n");
|
||||
else if (val == STORE_YUV422_8BIT)
|
||||
seq_puts(s, "YUV422 (8 bit)\n");
|
||||
else if (val == STORE_YUV422_10BIT)
|
||||
seq_puts(s, "YUV422 (10 bit)\n");
|
||||
else if (val == STORE_YUV444_8BIT)
|
||||
seq_puts(s, "YUV444 (8 bit)\n");
|
||||
else if (val == STORE_YUV420_16BIT)
|
||||
seq_puts(s, "YUV420 (16 bit)\n");
|
||||
else if (val == STORE_YUV422_16BIT)
|
||||
seq_puts(s, "YUV422 (16 bit)\n");
|
||||
else
|
||||
seq_puts(s, "UNKNOWN\n");
|
||||
|
||||
seq_printf(s, "Mode: %ux%u%s%u (%ux%u)",
|
||||
bt->width, bt->height, bt->interlaced ? "i" : "p",
|
||||
fps, htot, vtot);
|
||||
|
||||
seq_printf(s, "\t\thfp:%d hs:%d hbp:%d vfp:%d vs:%d vbp:%d\n",
|
||||
bt->hfrontporch, bt->hsync, bt->hbackporch,
|
||||
bt->vfrontporch, bt->vsync, bt->vbackporch);
|
||||
seq_printf(s, "Pixel Clk: %llu\n", bt->pixelclock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hdmirx_status_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, hdmirx_status_show, inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations hdmirx_status_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = hdmirx_status_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static void hdmirx_register_debugfs(struct device *dev,
|
||||
struct rk_hdmirx_dev *hdmirx_dev)
|
||||
{
|
||||
hdmirx_dev->debugfs_dir = debugfs_create_dir("hdmirx", NULL);
|
||||
if (IS_ERR(hdmirx_dev->debugfs_dir))
|
||||
return;
|
||||
|
||||
debugfs_create_file("ctrl", 0600, hdmirx_dev->debugfs_dir,
|
||||
hdmirx_dev, &hdmirx_ctrl_fops);
|
||||
debugfs_create_file("phy", 0600, hdmirx_dev->debugfs_dir,
|
||||
hdmirx_dev, &hdmirx_phy_fops);
|
||||
debugfs_create_file("status", 0600, hdmirx_dev->debugfs_dir,
|
||||
hdmirx_dev, &hdmirx_status_fops);
|
||||
}
|
||||
|
||||
static int hdmirx_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct v4l2_dv_timings timings_def = HDMIRX_DEFAULT_TIMING;
|
||||
@@ -2992,6 +3395,8 @@ static int hdmirx_probe(struct platform_device *pdev)
|
||||
cec_data.edid = edid_init_data;
|
||||
hdmirx_dev->cec = rk_hdmirx_cec_register(&cec_data);
|
||||
|
||||
hdmirx_register_debugfs(hdmirx_dev->dev, hdmirx_dev);
|
||||
|
||||
dev_info(dev, "%s driver probe ok!\n", dev_name(dev));
|
||||
|
||||
return 0;
|
||||
@@ -3019,6 +3424,8 @@ static int hdmirx_remove(struct platform_device *pdev)
|
||||
struct device *dev = &pdev->dev;
|
||||
struct rk_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
|
||||
|
||||
debugfs_remove_recursive(hdmirx_dev->debugfs_dir);
|
||||
|
||||
cancel_delayed_work(&hdmirx_dev->delayed_work_hotplug);
|
||||
cancel_delayed_work(&hdmirx_dev->delayed_work_res_change);
|
||||
cancel_delayed_work(&hdmirx_dev->delayed_work_audio);
|
||||
|
||||
Reference in New Issue
Block a user