usb: dwc_otg_310: map ep to corresponding TxFIFO number

In Dedicated FIFO mode, it uses a simple logic to assign
TxFIFO number for each active endpoint. But it doesn't
guarantee that the FIFO depth is suitable for the maxpacket
of the endpoint. We may meet ep TxFIFO problem if we use
a composite device with more than three functions.

In my test case, I configure an usb composite device with
four functions on rv108: Mass storage + ADB + Rndis + HID.

when the functions are enabled:
echo "mass_storage,ffs,rndis,hidg0" > /sys/class/android_usb/android0/functions

The mass_storage works abnormally because that the mass
storage gadget driver calls ep_enable operation at last,
and the ep1-in of mass_storage is assigned with TxFIFO
number 5. The FIFO mapping between the endpint addresses
and the TxFIFO number is:

Ep1-IN msc   bulk        => TxFIFO number 5, FIFO depth 64 Bytes
Ep3-IN adb   bulk        => TxFIFO number 1, FIFO depth 1024 Bytes
Ep5-IN rndis bulk        => TxFIFO number 3, FIFO depth 512 Bytes
Ep7-IN rndis interrupt   => TxFIFO number 2, FIFO depth 512 Bytes
Ep8-IN hid   interrupt   => TxFIFO number 4, FIFO depth 384 Bytes

This patch use a fixed mapping between the endpint addresses
and the TxFIFO number like this:

EP1-IN => TxFIFO number 1
EP3-IN => TxFIFO number 2
EP5-IN => TxFIFO number 3
EP7-IN => TxFIFO number 4
EP8-IN => TxFIFO number 5
EP9-IN => TxFIFO number 6

With this patch, in my test case (Mass storage+ ADB + Rndis + HID)
the FIFO mapping is:

Ep1-IN msc   bulk        => TxFIFO number 1, FIFO depth 1024 Bytes
Ep3-IN adb   bulk        => TxFIFO number 2, FIFO depth 512 Bytes
Ep5-IN rndis bulk        => TxFIFO number 3, FIFO depth 512 Bytes
Ep7-IN rndis interrupt   => TxFIFO number 4, FIFO depth 384 Bytes
Ep8-IN hid   interrupt   => TxFIFO number 5, FIFO depth 64 Bytes

Change-Id: Id00ed7e78d26d87b6c473ea84d1b1901ef25171e
Signed-off-by: William Wu <william.wu@rock-chips.com>
This commit is contained in:
William Wu
2018-07-10 18:04:48 +08:00
committed by Tao Huang
parent 72ea1ab611
commit 6e131f29b1

View File

@@ -1399,25 +1399,6 @@ uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t *pcd)
return retval;
}
/**
* This function assigns periodic Tx FIFO to an periodic EP
* in shared Tx FIFO mode
*/
static uint32_t assign_tx_fifo(dwc_otg_core_if_t *core_if)
{
uint32_t TxMsk = 1;
int i;
for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
if ((TxMsk & core_if->tx_msk) == 0) {
core_if->tx_msk |= TxMsk;
return i + 1;
}
TxMsk <<= 1;
}
return 0;
}
/**
* This function assigns periodic Tx FIFO to an periodic EP
* in shared Tx FIFO mode
@@ -1464,7 +1445,7 @@ static void release_tx_fifo(dwc_otg_core_if_t *core_if, uint32_t fifo_num)
int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t *pcd,
const uint8_t *ep_desc, void *usb_ep)
{
int num, dir;
int num, dir, fifo_map;
dwc_otg_pcd_ep_t *ep = NULL;
const usb_endpoint_descriptor_t *desc;
dwc_irqflags_t flags;
@@ -1497,6 +1478,7 @@ int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t *pcd,
for (i = 0; i < epcount; i++) {
if (num == pcd->in_ep[i].dwc_ep.num) {
ep = &pcd->in_ep[i];
fifo_map = i;
break;
}
}
@@ -1543,11 +1525,25 @@ int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t *pcd,
assign_perio_tx_fifo(GET_CORE_IF(pcd));
}
} else {
fifosize_data_t txfifosize;
dwc_otg_core_global_regs_t *global_regs =
GET_CORE_IF(pcd)->core_global_regs;
txfifosize.d32 =
DWC_READ_REG32(&global_regs->dtxfsiz[fifo_map]);
if ((txfifosize.b.depth * 4) < ep->dwc_ep.maxpacket)
DWC_WARN("No suitable fifo found for ep %d\n", num);
/*
* if Dedicated FIFOs mode is on then assign a Tx FIFO.
* According to register DIEPCTL.TxFNum, the TxFIFO Num
* index from 1, and the max FIFO Num is core_if->dev_if
* ->num_in_eps. We make one-to-one fixed mapping here:
* EP1-IN FIFO Num = 1, EP3-IN FIFO Num = 2,
* EP5-IN FIFO Num = 3, EP7-IN FIFO Num = 4,
* EP8-IN FIFO Num = 5, EP9-IN FIFO Num = 6.
*/
ep->dwc_ep.tx_fifo_num =
assign_tx_fifo(GET_CORE_IF(pcd));
ep->dwc_ep.tx_fifo_num = fifo_map + 1;
}
/* Calculating EP info controller base address */