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usb: dwc_otg_310: map ep to corresponding TxFIFO number
In Dedicated FIFO mode, it uses a simple logic to assign TxFIFO number for each active endpoint. But it doesn't guarantee that the FIFO depth is suitable for the maxpacket of the endpoint. We may meet ep TxFIFO problem if we use a composite device with more than three functions. In my test case, I configure an usb composite device with four functions on rv108: Mass storage + ADB + Rndis + HID. when the functions are enabled: echo "mass_storage,ffs,rndis,hidg0" > /sys/class/android_usb/android0/functions The mass_storage works abnormally because that the mass storage gadget driver calls ep_enable operation at last, and the ep1-in of mass_storage is assigned with TxFIFO number 5. The FIFO mapping between the endpint addresses and the TxFIFO number is: Ep1-IN msc bulk => TxFIFO number 5, FIFO depth 64 Bytes Ep3-IN adb bulk => TxFIFO number 1, FIFO depth 1024 Bytes Ep5-IN rndis bulk => TxFIFO number 3, FIFO depth 512 Bytes Ep7-IN rndis interrupt => TxFIFO number 2, FIFO depth 512 Bytes Ep8-IN hid interrupt => TxFIFO number 4, FIFO depth 384 Bytes This patch use a fixed mapping between the endpint addresses and the TxFIFO number like this: EP1-IN => TxFIFO number 1 EP3-IN => TxFIFO number 2 EP5-IN => TxFIFO number 3 EP7-IN => TxFIFO number 4 EP8-IN => TxFIFO number 5 EP9-IN => TxFIFO number 6 With this patch, in my test case (Mass storage+ ADB + Rndis + HID) the FIFO mapping is: Ep1-IN msc bulk => TxFIFO number 1, FIFO depth 1024 Bytes Ep3-IN adb bulk => TxFIFO number 2, FIFO depth 512 Bytes Ep5-IN rndis bulk => TxFIFO number 3, FIFO depth 512 Bytes Ep7-IN rndis interrupt => TxFIFO number 4, FIFO depth 384 Bytes Ep8-IN hid interrupt => TxFIFO number 5, FIFO depth 64 Bytes Change-Id: Id00ed7e78d26d87b6c473ea84d1b1901ef25171e Signed-off-by: William Wu <william.wu@rock-chips.com>
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@@ -1399,25 +1399,6 @@ uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t *pcd)
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return retval;
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}
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/**
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* This function assigns periodic Tx FIFO to an periodic EP
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* in shared Tx FIFO mode
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*/
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static uint32_t assign_tx_fifo(dwc_otg_core_if_t *core_if)
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{
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uint32_t TxMsk = 1;
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int i;
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for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
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if ((TxMsk & core_if->tx_msk) == 0) {
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core_if->tx_msk |= TxMsk;
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return i + 1;
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}
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TxMsk <<= 1;
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}
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return 0;
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}
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/**
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* This function assigns periodic Tx FIFO to an periodic EP
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* in shared Tx FIFO mode
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@@ -1464,7 +1445,7 @@ static void release_tx_fifo(dwc_otg_core_if_t *core_if, uint32_t fifo_num)
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int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t *pcd,
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const uint8_t *ep_desc, void *usb_ep)
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{
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int num, dir;
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int num, dir, fifo_map;
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dwc_otg_pcd_ep_t *ep = NULL;
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const usb_endpoint_descriptor_t *desc;
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dwc_irqflags_t flags;
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@@ -1497,6 +1478,7 @@ int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t *pcd,
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for (i = 0; i < epcount; i++) {
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if (num == pcd->in_ep[i].dwc_ep.num) {
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ep = &pcd->in_ep[i];
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fifo_map = i;
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break;
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}
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}
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@@ -1543,11 +1525,25 @@ int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t *pcd,
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assign_perio_tx_fifo(GET_CORE_IF(pcd));
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}
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} else {
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fifosize_data_t txfifosize;
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dwc_otg_core_global_regs_t *global_regs =
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GET_CORE_IF(pcd)->core_global_regs;
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txfifosize.d32 =
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DWC_READ_REG32(&global_regs->dtxfsiz[fifo_map]);
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if ((txfifosize.b.depth * 4) < ep->dwc_ep.maxpacket)
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DWC_WARN("No suitable fifo found for ep %d\n", num);
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/*
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* if Dedicated FIFOs mode is on then assign a Tx FIFO.
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* According to register DIEPCTL.TxFNum, the TxFIFO Num
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* index from 1, and the max FIFO Num is core_if->dev_if
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* ->num_in_eps. We make one-to-one fixed mapping here:
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* EP1-IN FIFO Num = 1, EP3-IN FIFO Num = 2,
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* EP5-IN FIFO Num = 3, EP7-IN FIFO Num = 4,
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* EP8-IN FIFO Num = 5, EP9-IN FIFO Num = 6.
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*/
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ep->dwc_ep.tx_fifo_num =
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assign_tx_fifo(GET_CORE_IF(pcd));
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ep->dwc_ep.tx_fifo_num = fifo_map + 1;
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}
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/* Calculating EP info controller base address */
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