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dmaengine: imx-sdma: remove BD_INTR for channel0
commit3f93a4f297upstream. It is possible for an irq triggered by channel0 to be received later after clks are disabled once firmware loaded during sdma probe. If that happens then clearing them by writing to SDMA_H_INTR won't work and the kernel will hang processing infinite interrupts. Actually, don't need interrupt triggered on channel0 since it's pollling SDMA_H_STATSTOP to know channel0 done rather than interrupt in current code, just clear BD_INTR to disable channel0 interrupt to avoid the above case. This issue was brought by commit1d069bfa3c("dmaengine: imx-sdma: ack channel 0 IRQ in the interrupt handler") which didn't take care the above case. Fixes:1d069bfa3c("dmaengine: imx-sdma: ack channel 0 IRQ in the interrupt handler") Cc: stable@vger.kernel.org #5.0+ Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reported-by: Sven Van Asbroeck <thesven73@gmail.com> Tested-by: Sven Van Asbroeck <thesven73@gmail.com> Reviewed-by: Michael Olbrich <m.olbrich@pengutronix.de> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
dd8f65a719
commit
6e8aa99a2e
@@ -632,7 +632,7 @@ static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
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spin_lock_irqsave(&sdma->channel_0_lock, flags);
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bd0->mode.command = C0_SETPM;
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bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
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bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
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bd0->mode.count = size / 2;
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bd0->buffer_addr = buf_phys;
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bd0->ext_buffer_addr = address;
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@@ -909,7 +909,7 @@ static int sdma_load_context(struct sdma_channel *sdmac)
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context->gReg[7] = sdmac->watermark_level;
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bd0->mode.command = C0_SETDM;
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bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
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bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
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bd0->mode.count = sizeof(*context) / 4;
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bd0->buffer_addr = sdma->context_phys;
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bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
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