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phy/rockchip: samsung-hdptx: modify pe/vs/pll configs for R216/R243/R324/R432

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According to the SI report, modify pe/vs configs of new
link rate R216/R243/R324/R432, which are configured to
nearby RBR/HBR/HBR2 configs in the past.

In addition, modify the pll configs to pass SSC test.

Change-Id: Ic10ea8289f47cfc93bd2c08231b76c68a6e4b4d2
Signed-off-by: damon.ding <damon.ding@rock-chips.com>
This commit is contained in:
damon.ding
2024-06-21 16:05:52 +08:00
committed by Tao Huang
parent a21414874a
commit 6e99cb3d84
1 changed files with 122 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

127
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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@@ -459,12 +459,96 @@ static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = {
}
};
static struct tx_drv_ctrl tx_drv_ctrl_r216_r243[4][4] = {
/* voltage swing 0, pre-emphasis 0->3 */
{
{ 0x0, 0x1, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x1, 0x2, 0x4, 0x4, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
{ 0x1, 0x3, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x3, 0x5, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 1, pre-emphasis 0->2 */
{
{ 0x1, 0x1, 0x4, 0x4, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
{ 0x2, 0x3, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x3, 0x4, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 2, pre-emphasis 0->1 */
{
{ 0x1, 0x1, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x1, 0x2, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 3, pre-emphasis 0 */
{
{ 0x3, 0x2, 0x2, 0x2, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
}
};
static struct tx_drv_ctrl tx_drv_ctrl_r324[4][4] = {
/* voltage swing 0, pre-emphasis 0->3 */
{
{ 0x1, 0x2, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x2, 0x3, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x2, 0x4, 0x5, 0x5, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x4, 0x6, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 1, pre-emphasis 0->2 */
{
{ 0x2, 0x2, 0x4, 0x4, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
{ 0x2, 0x3, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x4, 0x5, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 2, pre-emphasis 0->1 */
{
{ 0x2, 0x2, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x4, 0x4, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 3, pre-emphasis 0 */
{
{ 0x3, 0x2, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
}
};
static struct tx_drv_ctrl tx_drv_ctrl_r432[4][4] = {
/* voltage swing 0, pre-emphasis 0->3 */
{
{ 0x1, 0x2, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x2, 0x3, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x2, 0x4, 0x6, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x4, 0x6, 0x6, 0x6, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 1, pre-emphasis 0->2 */
{
{ 0x2, 0x2, 0x4, 0x4, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
{ 0x3, 0x4, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x5, 0x6, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 2, pre-emphasis 0->1 */
{
{ 0x2, 0x2, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x4, 0x4, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 3, pre-emphasis 0 */
{
{ 0x5, 0x3, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
}
};
/* pll configurations for link rate R216/R243/R324/R432 */
static struct tx_pll_ctrl tx_pll_ctrl_extra[4] = {
{ 0x5a, 0x01, 0x32, 0x00, 0x00, 0x00, 0x01, 0x04, 0x0f, 0x18 }, /* R216 */
{ 0x65, 0x01, 0x60, 0x00, 0x10, 0x01, 0x13, 0x18, 0x20, 0x0b }, /* R243 */
{ 0x87, 0x01, 0x21, 0x00, 0x00, 0x02, 0x03, 0x08, 0x0e, 0x1a }, /* R324 */
{ 0x5a, 0x00, 0x32, 0x00, 0x00, 0x00, 0x01, 0x01, 0x0f, 0x18 }, /* R432 */
static const struct tx_pll_ctrl tx_pll_ctrl_extra[4] = {
{ 0x5a, 0x01, 0x32, 0x00, 0x00, 0x00, 0x01, 0x04, 0x0d, 0x1d }, /* R216 */
{ 0x65, 0x01, 0x60, 0x00, 0x10, 0x01, 0x13, 0x18, 0x1c, 0x0d }, /* R243 */
{ 0x87, 0x01, 0x21, 0x00, 0x00, 0x02, 0x03, 0x08, 0x0d, 0x1c }, /* R324 */
{ 0x5a, 0x00, 0x32, 0x00, 0x00, 0x01, 0x01, 0x01, 0x0e, 0x1a }, /* R432 */
};
static int rockchip_hdptx_phy_parse_training_table(struct device *dev)
@@ -580,6 +664,17 @@ static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx,
break;
case 2160:
case 2430:
ctrl = &tx_drv_ctrl_r216_r243[dp->voltage[lane]][dp->pre[lane]];
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
LN_TX_SER_40BIT_EN_HBR,
FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1));
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),
LN_TX_JEQ_EVEN_CTRL_HBR,
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR, ctrl->tx_jeq_even_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),
LN_TX_JEQ_ODD_CTRL_HBR,
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR, ctrl->tx_jeq_odd_ctrl));
break;
case 2700:
ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]];
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
@@ -593,7 +688,29 @@ static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx,
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR, ctrl->tx_jeq_odd_ctrl));
break;
case 3240:
ctrl = &tx_drv_ctrl_r324[dp->voltage[lane]][dp->pre[lane]];
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
LN_TX_SER_40BIT_EN_HBR2,
FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1));
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),
LN_TX_JEQ_EVEN_CTRL_HBR2,
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2, ctrl->tx_jeq_even_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),
LN_TX_JEQ_ODD_CTRL_HBR2,
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2, ctrl->tx_jeq_odd_ctrl));
break;
case 4320:
ctrl = &tx_drv_ctrl_r432[dp->voltage[lane]][dp->pre[lane]];
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
LN_TX_SER_40BIT_EN_HBR2,
FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1));
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),
LN_TX_JEQ_EVEN_CTRL_HBR2,
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2, ctrl->tx_jeq_even_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),
LN_TX_JEQ_ODD_CTRL_HBR2,
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2, ctrl->tx_jeq_odd_ctrl));
break;
case 5400:
default:
ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]];