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clk: rockchip: rv1126: Fix MCLK_I2Sx_OUT2TO rate

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This patch allows user to set MCLK_I2Sx_OUT2IO freq
by CLK_SET_RATE_PARENT.

Change-Id: Ie8f3163726d34c7cf3ee206bbc1d0866049d6eda
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This commit is contained in:
Sugar Zhang
2020-11-02 10:34:30 +08:00
committed by Tao Huang
parent cb3d3f5e4c
commit 6f16cbd3e6
1 changed files with 4 additions and 4 deletions
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8
drivers/clk/rockchip/clk-rv1126.c
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@@ -744,10 +744,10 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
&rv1126_i2s0_rx_fracmux, RV1126_FRAC_MAX_PRATE),
GATE(MCLK_I2S0_RX, "mclk_i2s0_rx", "mclk_i2s0_rx_mux", 0,
RV1126_CLKGATE_CON(9), 10, GFLAGS),
COMPOSITE_NODIV(MCLK_I2S0_TX_OUT2IO, "mclk_i2s0_tx_out2io", mux_i2s0_tx_out2io_p, 0,
COMPOSITE_NODIV(MCLK_I2S0_TX_OUT2IO, "mclk_i2s0_tx_out2io", mux_i2s0_tx_out2io_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(30), 6, 1, MFLAGS,
RV1126_CLKGATE_CON(9), 13, GFLAGS),
COMPOSITE_NODIV(MCLK_I2S0_RX_OUT2IO, "mclk_i2s0_rx_out2io", mux_i2s0_rx_out2io_p, 0,
COMPOSITE_NODIV(MCLK_I2S0_RX_OUT2IO, "mclk_i2s0_rx_out2io", mux_i2s0_rx_out2io_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(30), 8, 1, MFLAGS,
RV1126_CLKGATE_CON(9), 14, GFLAGS),
@@ -762,7 +762,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
&rv1126_i2s1_fracmux, RV1126_FRAC_MAX_PRATE),
GATE(MCLK_I2S1, "mclk_i2s1", "mclk_i2s1_mux", 0,
RV1126_CLKGATE_CON(10), 3, GFLAGS),
COMPOSITE_NODIV(MCLK_I2S1_OUT2IO, "mclk_i2s1_out2io", mux_i2s1_out2io_p, 0,
COMPOSITE_NODIV(MCLK_I2S1_OUT2IO, "mclk_i2s1_out2io", mux_i2s1_out2io_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(31), 12, 1, MFLAGS,
RV1126_CLKGATE_CON(10), 4, GFLAGS),
GATE(HCLK_I2S2, "hclk_i2s2", "hclk_pdaudio", 0,
@@ -776,7 +776,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
&rv1126_i2s2_fracmux, RV1126_FRAC_MAX_PRATE),
GATE(MCLK_I2S2, "mclk_i2s2", "mclk_i2s2_mux", 0,
RV1126_CLKGATE_CON(10), 8, GFLAGS),
COMPOSITE_NODIV(MCLK_I2S2_OUT2IO, "mclk_i2s2_out2io", mux_i2s2_out2io_p, 0,
COMPOSITE_NODIV(MCLK_I2S2_OUT2IO, "mclk_i2s2_out2io", mux_i2s2_out2io_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(33), 10, 1, MFLAGS,
RV1126_CLKGATE_CON(10), 9, GFLAGS),