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media: rockchip: hdmirx: fix some source ced err.

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The boundary of different frequency points is set as the default value
to avoid CED interruption being triggered by mistake.

Signed-off-by: Wangqiang Guo <kay.guo@rock-chips.com>
Change-Id: I0b1257586d43e335496e87803628da72bc2a7c0c
This commit is contained in:
Wangqiang Guo
2022-09-17 03:21:50 +00:00
committed by Tao Huang
parent 78b085b196
commit 6feda272d3
2 changed files with 26 additions and 0 deletions
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16
drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c
View File

@@ -1338,6 +1338,22 @@ static void hdmirx_phy_config(struct rk_hdmirx_dev *hdmirx_dev)
hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0);
hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0);
hdmirx_phy_register_write(hdmirx_dev,
HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_3_REG,
CDR_SETTING_BOUNDARY_3_DEFAULT);
hdmirx_phy_register_write(hdmirx_dev,
HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_4_REG,
CDR_SETTING_BOUNDARY_4_DEFAULT);
hdmirx_phy_register_write(hdmirx_dev,
HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_5_REG,
CDR_SETTING_BOUNDARY_5_DEFAULT);
hdmirx_phy_register_write(hdmirx_dev,
HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_6_REG,
CDR_SETTING_BOUNDARY_6_DEFAULT);
hdmirx_phy_register_write(hdmirx_dev,
HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_7_REG,
CDR_SETTING_BOUNDARY_7_DEFAULT);
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_PDDQ, 0);
if (wait_reg_bit_status(hdmirx_dev, PHY_STATUS, PDDQ_ACK, 0, false, 10))
dev_err(dev, "%s wait pddq ack failed!\n", __func__);

10
drivers/media/platform/rockchip/hdmirx/rk_hdmirx.h
View File

@@ -51,6 +51,16 @@
#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_FSM_CONFIG 0x20c4
#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_ADAPT_REF_FOM 0x20c7
#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_3_REG 0x20e9
#define CDR_SETTING_BOUNDARY_3_DEFAULT 0x52da
#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_4_REG 0x20ea
#define CDR_SETTING_BOUNDARY_4_DEFAULT 0x43cd
#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_5_REG 0x20eb
#define CDR_SETTING_BOUNDARY_5_DEFAULT 0x35b3
#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_6_REG 0x20fb
#define CDR_SETTING_BOUNDARY_6_DEFAULT 0x2799
#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_7_REG 0x20fc
#define CDR_SETTING_BOUNDARY_7_DEFAULT 0x1b65
#define RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e
#define RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e