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clk: rockchip: rv1126: Fix capture pwm clock name

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Change-Id: I80ae5054d2f7cb0f8e627501e9921bc4dca63c1e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2020-04-15 09:43:12 +08:00
committed by Tao Huang
parent 0656092399
commit 70cde67391
2 changed files with 3 additions and 4 deletions
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6
drivers/clk/rockchip/clk-rv1126.c
View File

@@ -364,14 +364,14 @@ static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
RV1126_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
RV1126_PMU_CLKGATE_CON(0), 10, GFLAGS),
GATE(CLK_CAPTURE_PWM0, "pclk_capture_pwm0", "xin24m", 0,
GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
RV1126_PMU_CLKGATE_CON(1), 2, GFLAGS),
GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
RV1126_PMU_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE(CLK_PWM0, "clk_pwm0", mux_xin24m_gpll_p, 0,
RV1126_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_PMU_CLKGATE_CON(1), 1, GFLAGS),
GATE(CLK_CAPTURE_PWM1, "pclk_capture_pwm1", "xin24m", 0,
GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
RV1126_PMU_CLKGATE_CON(1), 5, GFLAGS),
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_pdpmu", 0,
RV1126_PMU_CLKGATE_CON(1), 3, GFLAGS),
@@ -618,7 +618,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
RV1126_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(4), 3, GFLAGS),
GATE(PCLK_CAPTURE_PWM2, "pclk_capture_pwm2", "xin24m", 0,
GATE(CLK_CAPTURE_PWM2, "clk_capture_pwm2", "xin24m", 0,
RV1126_CLKGATE_CON(4), 6, GFLAGS),
GATE(PCLK_PWM2, "pclk_pwm2", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(4), 4, GFLAGS),

1
include/dt-bindings/clock/rv1126-cru.h
View File

@@ -319,7 +319,6 @@
#define PCLK_I2C4 257
#define PCLK_I2C5 258
#define PCLK_SPI1 259
#define PCLK_CAPTURE_PWM2 260
#define PCLK_PWM2 261
#define PCLK_GPIO1 262
#define PCLK_GPIO2 263