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net: phy: dp83867: Check if the phy is in an internal testing mode

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The DP83867 seems to be always in an internal mode on our Board.
This mode can cause connection problems. We disable this mode.

Unfortunately, Register 0x31 Bit 7 is not documented and marked as reserved.
If Bit 7 is set, phy is in the internal testing mode.

Change-Id: I5d3435fcfea0e1af7c4d5ee510c249f41211f223
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
This commit is contained in:
Wadim Egorov
2017-03-23 15:31:26 +01:00
committed by Tao Huang
parent 988a354947
commit 70d9feffcd
1 changed files with 10 additions and 0 deletions
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10
drivers/net/phy/dp83867.c
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@@ -317,6 +317,16 @@ static int dp83867_config_init(struct phy_device *phydev)
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val);
}
/* Check if the PHY is an internal testing mode.
* This mode can cause connection problems.
*/
val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR);
if (val & BIT(7)) {
val &= ~BIT(7);
phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
val);
}
/* Disable FORCE_LINK_GOOD */
val = phy_read(phydev, MII_DP83867_PHYCTRL);
if (val & MII_DP83867_PHYCTRL_FORCE_LINK_GOOD) {