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hdmirx: modify audio pll setting [1/1]

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PD#172587

Problem:
1.audio divider it's not work

Solution:
1.modify audio top clk measure
2.modify audio divider clk source
3.modify audio divider band gap

Verify:
tl1

Change-Id: Iea254f043531f31383a727c58b4d992dd39ff2ce
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
This commit is contained in:
Yong Qin
2018-11-12 15:45:46 +08:00
committed by Luke Go
parent 04fbabda4e
commit 70e16d437c
3 changed files with 13 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
View File

@@ -2414,10 +2414,10 @@ void rx_aud_pll_ctl(bool en)
if (en) {
/* AUD_CLK=N/CTS*TMDS_CLK */
/* bandgap enable */
tmp = rd_reg_hhi(HHI_VDAC_CNTL1);
wr_reg_hhi(HHI_VDAC_CNTL1, tmp|0x80);
wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x40000540);
#if 0
wr_reg_hhi(HHI_VDAC_CNTL0, 0x906001);
wr_reg_hhi(HHI_VDAC_CNTL1, 0x0);
wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x40001540);
#if 1
/* use mpll */
tmp = 0;
tmp |= 2 << 2; /* 0:tmds_clk 1:ref_clk 2:mpll_clk */
@@ -2433,7 +2433,7 @@ void rx_aud_pll_ctl(bool en)
wr_reg_hhi(HHI_AUD_PLL_CNTL3, 0);
#endif
rx_pr("aud div=%d\n", rd_reg_hhi(HHI_AUD_PLL_CNTL3));
wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x60000540);
wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x60001540);
rx_pr("audio pll lock:0x%x\n",
rd_reg_hhi(HHI_AUD_PLL_CNTL_I));
/*rx_audio_pll_sw_update();*/
@@ -2661,8 +2661,8 @@ unsigned int rx_get_clock(enum measure_clk_top_e clk_src)
uint32_t clock = 0;
uint32_t tmp_data = 0;
uint32_t meas_cycles = 0;
uint32_t tmp_data2 = 0;
ulong audclk = 0;
uint64_t tmp_data2 = 0;
uint32_t audclk = 0;
if (clk_src == TOP_HDMI_TMDSCLK)
tmp_data = hdmirx_rd_top(TOP_METER_HDMI_STAT);
@@ -2674,7 +2674,7 @@ unsigned int rx_get_clock(enum measure_clk_top_e clk_src)
/*get audio clk*/
tmp_data = hdmirx_rd_top(TOP_AUDMEAS_REF_CYCLES_STAT0);
tmp_data2 = hdmirx_rd_top(TOP_AUDMEAS_REF_CYCLES_STAT1);
audclk = (tmp_data2 & 0xffff)|tmp_data;
audclk = ((tmp_data2 & 0xffff) << 32)|tmp_data;
if (tmp_data2 & (0x1 << 17))
audclk = (24000 * 65536) / ((audclk + 1)/1000);
else
@@ -2811,18 +2811,18 @@ unsigned int rx_measure_clock(enum measure_clk_src_e clksrc)
clock = meson_clk_measure(29);
} else if (clksrc == MEASURE_CLK_AUD_PLL) {
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
clock = meson_clk_measure(74);
clock = meson_clk_measure(74);/*audio vid out*/
else
clock = meson_clk_measure(24);
} else if (clksrc == MEASURE_CLK_AUD_DIV) {
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
clock = meson_clk_measure(60);
clock = meson_clk_measure(67);/*apll_clk_audio*/
else
clock = meson_clk_measure(98);
} else if (clksrc == MEASURE_CLK_MPLL) {
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
clock = meson_clk_measure(67);/*apll_clk_audio*/
clock = meson_clk_measure(29);/*apll_clk_out_div*/
else
clock = meson_clk_measure(27);
} else if (clksrc == MEASURE_CLK_ESM) {

1
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
View File

@@ -39,6 +39,7 @@
#define HHI_GCLK_MPEG0 (0x50 << 2) /* (0xC883C000 + 0x140) */
#define HHI_HDMIRX_CLK_CNTL 0x200 /* (0xC883C000 + 0x200) */
#define HHI_HDMIRX_AUD_CLK_CNTL 0x204 /* 0x1081 */
#define HHI_VDAC_CNTL0 (0xbb * 4)
#define HHI_VDAC_CNTL1 (0xbc * 4)
#define HHI_AUD_PLL_CNTL (0xf8 * 4)
#define HHI_AUD_PLL_CNTL2 (0xf9 * 4)

2
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
View File

@@ -2926,7 +2926,7 @@ static void dump_clk_status(void)
rx_measure_clock(MEASURE_CLK_PIXEL));
rx_pr("audio clock = %d\n",
rx_measure_clock(MEASURE_CLK_AUD_PLL));
rx_pr("aud div clock = %d\n",
rx_pr("aud clk in = %d\n",
rx_measure_clock(MEASURE_CLK_AUD_DIV));
rx_pr("mpll clock = %d\n",
rx_measure_clock(MEASURE_CLK_MPLL));