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ARM: dts: rockchip: rk3506: add DMAC/UART nodes

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Change-Id: Id804041ae57f7e8551e0ab4f3d9233b74dbebc42
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
This commit is contained in:
Huibin Hong
2024-06-05 16:01:30 +08:00
committed by Tao Huang
parent 7a0978f782
commit 71a4b6dca7
1 changed files with 94 additions and 1 deletions
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95
arch/arm/boot/dts/rk3506.dtsi
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@@ -23,6 +23,11 @@
gpio3 = &gpio3;
gpio4 = &gpio4;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
spi2 = &fspi;
};
@@ -105,13 +110,87 @@
clock-frequency = <24000000>;
};
dmac0: dma-controller@ff000000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xff000000 0x4000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_DMAC0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
arm,pl330-periph-burst;
};
dmac1: dma-controller@ff008000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xff008000 0x4000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_DMAC1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
arm,pl330-periph-burst;
};
uart0: serial@ff0a0000 {
compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart";
reg = <0xff0a0000 0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 4>, <&dmac0 5>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer_pins>;
status = "disabled";
};
uart1: serial@ff0b0000 {
compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart";
reg = <0xff0b0000 0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 6>, <&dmac0 7>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
status = "disabled";
};
uart2: serial@ff0c0000 {
compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart";
reg = <0xff0c0000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 8>, <&dmac0 9>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
status = "disabled";
};
uart3: serial@ff0d0000 {
compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart";
reg = <0xff0d0000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 10>, <&dmac0 11>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
status = "disabled";
};
uart4: serial@ff0e0000 {
compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart";
reg = <0xff0e0000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac1 12>, <&dmac1 13>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
status = "disabled";
};
@@ -309,6 +388,20 @@
reg = <0xff4d8000 0x8000>;
};
uart5: serial@ff4e0000 {
compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart";
reg = <0xff4e0000 0x100>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac1 14>, <&dmac1 15>;
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart5m0_xfer_pins &uart5m0_ctsn_pins &uart5m0_rtsn_pins>;
status = "disabled";
};
gic: interrupt-controller@ff581000 {
compatible = "arm,gic-400";
reg = <0xff581000 0x1000>,