shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-06 02:50:49 +09:00
Code Issues Packages Projects Releases Wiki Activity

ethernet: stmmac: dwmac-rk: Add GMAC support for RK3576

Browse Source 
Add constants and callback functions for the dwmac on RK3576 soc.
As can be seen, the base structure is the same.

Change-Id: If5081998d98a20c6efe14992e00b719ae0ad0dd2
Signed-off-by: David Wu <david.wu@rock-chips.com>
This commit is contained in:
David Wu
2024-01-24 19:03:26 +08:00
committed by Tao Huang
parent b25f38ede4
commit 71bd521294
2 changed files with 158 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
View File

@@ -27,6 +27,7 @@ select:
- rockchip,rk3528-gmac
- rockchip,rk3562-gmac
- rockchip,rk3568-gmac
- rockchip,rk3576-gmac
- rockchip,rk3588-gmac
- rockchip,rv1106-gmac
- rockchip,rv1108-gmac
@@ -58,6 +59,7 @@ properties:
- rockchip,rk3528-gmac
- rockchip,rk3562-gmac
- rockchip,rk3568-gmac
- rockchip,rk3576-gmac
- rockchip,rk3588-gmac
- rockchip,rv1106-gmac
- rockchip,rv1126-gmac

156
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
View File

@@ -1904,6 +1904,159 @@ static const struct rk_gmac_ops rk3568_ops = {
},
};
/* VCCIO0_1_3_IOC */
#define RK3576_VCCIO0_1_3_IOC_CON2 0X6408
#define RK3576_VCCIO0_1_3_IOC_CON3 0X640c
#define RK3576_VCCIO0_1_3_IOC_CON4 0X6410
#define RK3576_VCCIO0_1_3_IOC_CON5 0X6414
#define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
#define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
#define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
#define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
#define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
#define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
/* SDGMAC_GRF */
#define RK3576_GRF_GMAC_CON0 0X0020
#define RK3576_GRF_GMAC_CON1 0X0024
#define RK3576_GMAC_RMII_MODE GRF_BIT(3)
#define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3)
#define RK3576_GMAC_CLK_SELET_IO GRF_BIT(7)
#define RK3576_GMAC_CLK_SELET_CRU GRF_CLR_BIT(7)
#define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5)
#define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5)
#define RK3576_GMAC_CLK_RGMII_DIV1 \
(GRF_CLR_BIT(6) | GRF_CLR_BIT(5))
#define RK3576_GMAC_CLK_RGMII_DIV5 \
(GRF_BIT(6) | GRF_BIT(5))
#define RK3576_GMAC_CLK_RGMII_DIV50 \
(GRF_BIT(6) | GRF_CLR_BIT(5))
#define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4)
#define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4)
static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
struct device *dev = &bsp_priv->pdev->dev;
unsigned int offset_con;
if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
return;
}
offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
RK3576_GRF_GMAC_CON0;
regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE);
offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 :
RK3576_VCCIO0_1_3_IOC_CON2;
/* m0 && m1 delay enabled */
regmap_write(bsp_priv->php_grf, offset_con,
DELAY_ENABLE(RK3576, tx_delay, rx_delay));
regmap_write(bsp_priv->php_grf, offset_con + 0x4,
DELAY_ENABLE(RK3576, tx_delay, rx_delay));
/* m0 && m1 delay value */
regmap_write(bsp_priv->php_grf, offset_con,
DELAY_VALUE(RK3576, tx_delay, rx_delay));
regmap_write(bsp_priv->php_grf, offset_con + 0x4,
DELAY_VALUE(RK3576, tx_delay, rx_delay));
}
static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
{
struct device *dev = &bsp_priv->pdev->dev;
unsigned int offset_con;
if (IS_ERR(bsp_priv->php_grf)) {
dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__);
return;
}
offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
RK3576_GRF_GMAC_CON0;
regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE);
}
static void rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
{
struct device *dev = &bsp_priv->pdev->dev;
unsigned int val = 0, offset_con;
switch (speed) {
case 10:
if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
val = RK3576_GMAC_CLK_RMII_DIV20;
else
val = RK3576_GMAC_CLK_RGMII_DIV50;
break;
case 100:
if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
val = RK3576_GMAC_CLK_RMII_DIV2;
else
val = RK3576_GMAC_CLK_RGMII_DIV5;
break;
case 1000:
if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
val = RK3576_GMAC_CLK_RGMII_DIV1;
else
goto err;
break;
default:
goto err;
}
offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
RK3576_GRF_GMAC_CON0;
regmap_write(bsp_priv->grf, offset_con, val);
return;
err:
dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
}
static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
bool enable)
{
unsigned int val = input ? RK3576_GMAC_CLK_SELET_IO :
RK3576_GMAC_CLK_SELET_CRU;
unsigned int offset_con;
val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE :
RK3576_GMAC_CLK_RMII_GATE;
offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
RK3576_GRF_GMAC_CON0;
regmap_write(bsp_priv->grf, offset_con, val);
}
static const struct rk_gmac_ops rk3576_ops = {
.set_to_rgmii = rk3576_set_to_rgmii,
.set_to_rmii = rk3576_set_to_rmii,
.set_rgmii_speed = rk3576_set_gmac_speed,
.set_rmii_speed = rk3576_set_gmac_speed,
.set_clock_selection = rk3576_set_clock_selection,
.regs_valid = true,
.regs = {
0x2a220000, /* gmac0 */
0x2a230000, /* gmac1 */
0x0, /* sentinel */
},
};
/* sys_grf */
#define RK3588_GRF_GMAC_CON7 0X031c
#define RK3588_GRF_GMAC_CON8 0X0320
@@ -3001,6 +3154,9 @@ static const struct of_device_id rk_gmac_dwmac_match[] = {
#ifdef CONFIG_CPU_RK3568
{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
#endif
#ifdef CONFIG_CPU_RK3576
{ .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
#endif
#ifdef CONFIG_CPU_RK3588
{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
#endif