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arm64: dts: imx8mq-librem5: update pinctrl to match dtschema
The dtschema requires 'grp' in the end, so update the name. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
@@ -667,7 +667,7 @@
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>;
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};
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pinctrl_spkamp: spkamp {
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pinctrl_spkamp: spkampgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x81 /* MUTE */
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>;
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@@ -686,7 +686,7 @@
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
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@@ -703,7 +703,7 @@
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
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@@ -733,7 +733,7 @@
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
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@@ -746,7 +746,7 @@
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
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