Merge commit 'b80127f10714a3d0de790b584af79dc73f5fd3e5'

* commit 'b80127f10714a3d0de790b584af79dc73f5fd3e5': mmc: sdhci-of-dwcmshc: set RK_TAP_VALUE_SEL flag for rk3568 and rk3588 media: i2c: rk628: fix mipi dphy1 init by chip version arm64: dts: rockchip: rk3576-ebook: enable uboot charge drm/rockchip: vop2: enable vop urgency signal output for rk3576 drm/rockchip: drv: remove unused rockchip_drm_get_dclk_by_width() drm/rockchip: vop2: use pixel rate to verify vp performance drm/rockchip: vop2: add more debug info arm64: dts: rockchip: rk3576: add second pd RK3576_PD_VO0 for vopl drm/rockchip: vop: add multiple power domains support regulator: rk806: Solve PWRCTL2/3 level inconsistency in the suspend/resume regulator: rk806: Solve the initialization of non integer multiple step voltage power: supply: rockchip_charger_manager: supports JEITA profile arm64: dts: rockchip: rk3576-evb: enable i2c2 ARM: dts: rockchip: rv1126: Fixes warning in unit address of drm-logo ARM: dts: rockchip: Fixes warning in unit address of drm-logo arm64: dts: rockchip: rk3562: Fixes warning in unit address of drm-logo arm64: dts: rockchip: rk3328-evb: Fixes warning in unit address of drm-logo arm64: dts: rockchip: rk3308: Fixes warning in unit address of drm-logo arm64: dts: rockchip: Fixes warning in unit address of drm-logo Change-Id: I61a9cfa872c7990f12a8e9c1ff6534c186f01f56
2026-06-11 13:27:06 +09:00 · 2024-04-01 20:46:00 +08:00
parent 4923c5d7fd b80127f107
commit 72aa2b7227
43 changed files with 204 additions and 98 deletions
--- a/arch/arm/boot/dts/rk3128h-box.dtsi
+++ b/arch/arm/boot/dts/rk3128h-box.dtsi
@@ -35,7 +35,7 @@
 		#size-cells = <1>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0>;
 		};
--- a/arch/arm/boot/dts/rk312x-android.dtsi
+++ b/arch/arm/boot/dts/rk312x-android.dtsi
@@ -54,7 +54,7 @@
 			pmsg-size = <0x50000>;
 		};

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0>;
 		};
--- a/arch/arm/boot/dts/rk322x-android.dtsi
+++ b/arch/arm/boot/dts/rk322x-android.dtsi
@@ -73,7 +73,7 @@
 		#size-cells = <1>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0>;
 		};
--- a/arch/arm/boot/dts/rk3288-android.dtsi
+++ b/arch/arm/boot/dts/rk3288-android.dtsi
@@ -128,7 +128,7 @@
 			pmsg-size = <0x50000>;
 		};

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm/boot/dts/rk3288-firefly-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-firefly-rk808.dts
@@ -158,7 +158,7 @@
 			pmsg-size = <0x0 0x50000>;
 		};

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm/boot/dts/rk3288-linux.dtsi
+++ b/arch/arm/boot/dts/rk3288-linux.dtsi
@@ -85,7 +85,7 @@
 			reg = <0x0 0x8000000 0x0 0xF0000>;
 		};

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm/boot/dts/rv1103g-evb-mcu-display-v11.dts
+++ b/arch/arm/boot/dts/rv1103g-evb-mcu-display-v11.dts
@@ -62,7 +62,7 @@
 			linux,cma-default;
 		};

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0>;
 		};
--- a/arch/arm/boot/dts/rv1106-evb-ext-mcu-v10.dtsi
+++ b/arch/arm/boot/dts/rv1106-evb-ext-mcu-v10.dtsi
@@ -59,7 +59,7 @@
 			linux,cma-default;
 		};

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0>;
 		};
--- a/arch/arm/boot/dts/rv1106-evb-ext-mcu-v20.dtsi
+++ b/arch/arm/boot/dts/rv1106-evb-ext-mcu-v20.dtsi
@@ -49,7 +49,7 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0>;
 		};
--- a/arch/arm/boot/dts/rv1106-evb-ext-rgb-v10.dtsi
+++ b/arch/arm/boot/dts/rv1106-evb-ext-rgb-v10.dtsi
@@ -97,7 +97,7 @@
 			linux,cma-default;
 		};

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0>;
 		};
--- a/arch/arm/boot/dts/rv1106g-evb2-v11-trailcam-emmc.dts
+++ b/arch/arm/boot/dts/rv1106g-evb2-v11-trailcam-emmc.dts
@@ -98,7 +98,7 @@
 			linux,cma-default;
 		};
 */
-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0>;
 		};
--- a/arch/arm/boot/dts/rv1126.dtsi
+++ b/arch/arm/boot/dts/rv1126.dtsi
@@ -384,7 +384,7 @@
 			linux,cma-default;
 		};

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/px30-android.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-android.dtsi
@@ -44,7 +44,7 @@
 		#size-cells = <2>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi
@@ -112,7 +112,7 @@
 		#size-cells = <2>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -399,7 +399,7 @@
 		#size-cells = <2>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3326-linux.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3326-linux.dtsi
@@ -35,7 +35,7 @@
 		#size-cells = <2>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3328-android.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328-android.dtsi
@@ -35,7 +35,7 @@
 		#size-cells = <2>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
@@ -38,7 +38,7 @@
 		#size-cells = <2>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3358-linux.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3358-linux.dtsi
@@ -29,7 +29,7 @@
 		#size-cells = <2>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi
@@ -25,7 +25,7 @@
 		#size-cells = <2>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
@@ -48,7 +48,7 @@
 		#size-cells = <2>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly-android.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly-android.dts
@@ -114,7 +114,7 @@
 		#size-cells = <2>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3399-linux.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-linux.dtsi
@@ -25,7 +25,7 @@
 		#size-cells = <2>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3528-android.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528-android.dtsi
@@ -41,12 +41,12 @@
 			linux,cma-default;
 		};

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};

-		drm_cubic_lut: drm-cubic-lut@00000000 {
+		drm_cubic_lut: drm-cubic-lut@0 {
 			compatible = "rockchip,drm-cubic-lut";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3528-linux.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528-linux.dtsi
@@ -34,12 +34,12 @@
 		#size-cells = <2>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};

-		drm_cubic_lut: drm-cubic-lut@00000000 {
+		drm_cubic_lut: drm-cubic-lut@0 {
 			compatible = "rockchip,drm-cubic-lut";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
@@ -578,7 +578,7 @@
 		#size-cells = <2>;
 		ranges;

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
@@ -588,7 +588,7 @@
 			reg = <0x0 0x0 0x0 0x0>;
 		};

-		drm_cubic_lut: drm-cubic-lut@00000000 {
+		drm_cubic_lut: drm-cubic-lut@0 {
 			compatible = "rockchip,drm-cubic-lut";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3576-ebook-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3576-ebook-v10.dts
@@ -56,6 +56,18 @@
 		};
 	};

+	charge-animation {
+		compatible = "rockchip,uboot-charge";
+		rockchip,uboot-charge-on = <1>;
+		rockchip,android-charge-on = <0>;
+		rockchip,uboot-low-power-voltage = <3450>;
+		rockchip,screen-on-voltage = <3500>;
+		rockchip,uboot-exit-charge-level = <2>;
+		rockchip,uboot-exit-charge-voltage = <3500>;
+		rockchip,uboot-exit-charge-auto = <1>;
+		status = "okay";
+	};
+
 	charger-manager {
 		compatible = "rockchip-charger-manager";
 		cm-name = "battery";
--- a/arch/arm64/boot/dts/rockchip/rk3576-ebook-x3-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3576-ebook-x3-v10.dts
@@ -66,6 +66,18 @@
 		};
 	};

+	charge-animation {
+		compatible = "rockchip,uboot-charge";
+		rockchip,uboot-charge-on = <1>;
+		rockchip,android-charge-on = <0>;
+		rockchip,uboot-low-power-voltage = <3450>;
+		rockchip,screen-on-voltage = <3500>;
+		rockchip,uboot-exit-charge-level = <2>;
+		rockchip,uboot-exit-charge-voltage = <3500>;
+		rockchip,uboot-exit-charge-auto = <1>;
+		status = "okay";
+	};
+
 	charger-manager {
 		compatible = "rockchip-charger-manager";
 		cm-name = "battery";
--- a/arch/arm64/boot/dts/rockchip/rk3576-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576-evb.dtsi
@@ -591,6 +591,8 @@
 };

 &i2c2 {
+	status = "okay";
+
 	hym8563: hym8563@51 {
 		compatible = "haoyu,hym8563";
 		reg = <0x51>;
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -2190,7 +2190,8 @@
 		interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru ACLK_EBC>, <&cru DCLK_EBC>, <&cru HCLK_EBC>;
 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
-		power-domains = <&power RK3576_PD_VPU>;
+		power-domains = <&power RK3576_PD_VPU>, <&power RK3576_PD_VO0>;
+		power-domain-names = "pd0", "pd1";
 		rockchip,grf = <&ioc_grf>;
 		rockchip,vo0-grf = <&vo0_grf>;
 		status = "disabled";
--- a/arch/arm64/boot/dts/rockchip/rk3588-android.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-android.dtsi
@@ -72,12 +72,12 @@
 			linux,cma-default;
 		};

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};

-		drm_cubic_lut: drm-cubic-lut@00000000 {
+		drm_cubic_lut: drm-cubic-lut@0 {
 			compatible = "rockchip,drm-cubic-lut";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi
@@ -79,12 +79,12 @@
 			linux,cma-default;
 		};

-		drm_logo: drm-logo@00000000 {
+		drm_logo: drm-logo@0 {
 			compatible = "rockchip,drm-logo";
 			reg = <0x0 0x0 0x0 0x0>;
 		};

-		drm_cubic_lut: drm-cubic-lut@00000000 {
+		drm_cubic_lut: drm-cubic-lut@0 {
 			compatible = "rockchip,drm-cubic-lut";
 			reg = <0x0 0x0 0x0 0x0>;
 		};
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -450,40 +450,6 @@ int rockchip_drm_add_modes_noedid(struct drm_connector *connector)
 }
 EXPORT_SYMBOL(rockchip_drm_add_modes_noedid);

-static const struct rockchip_drm_width_dclk {
-	int width;
-	u32 dclk_khz;
-} rockchip_drm_dclk[] = {
-	{1920, 148500},
-	{2048, 200000},
-	{2560, 280000},
-	{3840, 594000},
-	{4096, 594000},
-	{7680, 2376000},
-};
-
-u32 rockchip_drm_get_dclk_by_width(int width)
-{
-	int i = 0;
-	u32 dclk_khz;
-
-	for (i = 0; i < ARRAY_SIZE(rockchip_drm_dclk); i++) {
-		if (width == rockchip_drm_dclk[i].width) {
-			dclk_khz = rockchip_drm_dclk[i].dclk_khz;
-			break;
-		}
-	}
-
-	if (i == ARRAY_SIZE(rockchip_drm_dclk)) {
-		DRM_ERROR("Can't not find %d width solution and use 148500 khz as max dclk\n", width);
-
-		dclk_khz = 148500;
-	}
-
-	return dclk_khz;
-}
-EXPORT_SYMBOL(rockchip_drm_get_dclk_by_width);
-
 static const char * const color_encoding_name[] = {
 	[DRM_COLOR_YCBCR_BT601] = "BT.601",
 	[DRM_COLOR_YCBCR_BT709] = "BT.709",
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -599,7 +599,6 @@ int rockchip_drm_add_modes_noedid(struct drm_connector *connector);
 void rockchip_drm_te_handle(struct drm_crtc *crtc);
 void drm_mode_convert_to_split_mode(struct drm_display_mode *mode);
 void drm_mode_convert_to_origin_mode(struct drm_display_mode *mode);
-u32 rockchip_drm_get_dclk_by_width(int width);
 const char *rockchip_drm_get_color_encoding_name(enum drm_color_encoding encoding);
 const char *rockchip_drm_get_color_range_name(enum drm_color_range range);
 #if IS_REACHABLE(CONFIG_DRM_ROCKCHIP)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -18,6 +18,7 @@
 #include <linux/of_device.h>
 #include <linux/overflow.h>
 #include <linux/platform_device.h>
+#include <linux/pm_domain.h>
 #include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 #include <linux/reset.h>
@@ -223,6 +224,8 @@ struct vop_win {
 struct vop {
 	struct rockchip_crtc rockchip_crtc;
 	struct device *dev;
+	struct device *genpd_dev0;
+	struct device *genpd_dev1;
 	struct drm_device *drm_dev;
 	struct dentry *debugfs;
 	struct drm_info_list *debugfs_files;
@@ -1594,10 +1597,28 @@ static void vop_power_enable(struct drm_crtc *crtc)
 		goto err_disable_dclk;
 	}

-	ret = pm_runtime_get_sync(vop->dev);
+	if (vop->genpd_dev0) {
+		ret = pm_runtime_resume_and_get(vop->genpd_dev0);
+		if (ret < 0) {
+			dev_err(vop->dev,
+				"failed to get pm runtime for pd0, ret = %d\n", ret);
+			goto err_disable_aclk;
+		}
+	}
+
+	if (vop->genpd_dev1) {
+		ret = pm_runtime_resume_and_get(vop->genpd_dev1);
+		if (ret < 0) {
+			dev_err(vop->dev,
+				"failed to get pm runtime for pd1, ret = %d\n", ret);
+			goto err_put_genpd_dev0;
+		}
+	}
+
+	ret = pm_runtime_resume_and_get(vop->dev);
 	if (ret < 0) {
 		dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
-		return;
+		goto err_put_genpd_dev1;
 	}

 	vop_regsbak(vop);
@@ -1616,6 +1637,12 @@ static void vop_power_enable(struct drm_crtc *crtc)

 	return;

+err_put_genpd_dev1:
+	pm_runtime_put_sync(vop->genpd_dev1);
+err_put_genpd_dev0:
+	pm_runtime_put_sync(vop->genpd_dev0);
+err_disable_aclk:
+	clk_disable_unprepare(vop->aclk);
 err_disable_dclk:
 	clk_disable_unprepare(vop->dclk);
 err_disable_hclk:
@@ -1724,6 +1751,13 @@ static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
 	}

 	pm_runtime_put_sync(vop->dev);
+
+	if (vop->genpd_dev1)
+		pm_runtime_put_sync(vop->genpd_dev1);
+
+	if (vop->genpd_dev0)
+		pm_runtime_put_sync(vop->genpd_dev0);
+
 	clk_disable_unprepare(vop->dclk);
 	clk_disable_unprepare(vop->aclk);
 	clk_disable_unprepare(vop->hclk);
@@ -5218,6 +5252,7 @@ static int vop_bind(struct device *dev, struct device *master, void *data)
 	struct drm_device *drm_dev = data;
 	struct vop *vop;
 	struct resource *res;
+	struct device *virt_dev = NULL;
 	size_t alloc_size;
 	int ret, irq, i;
 	int num_wins = 0;
@@ -5330,6 +5365,14 @@ static int vop_bind(struct device *dev, struct device *master, void *data)

 	pm_runtime_enable(&pdev->dev);

+	if (of_count_phandle_with_args(dev->of_node, "power-domains", "#power-domain-cells") > 1) {
+		virt_dev = dev_pm_domain_attach_by_name(dev, "pd0");
+		if (!IS_ERR(virt_dev))
+			vop->genpd_dev0 = virt_dev;
+		virt_dev = dev_pm_domain_attach_by_name(dev, "pd1");
+		if (!IS_ERR(virt_dev))
+			vop->genpd_dev1 = virt_dev;
+	}

 	mcu = of_get_child_by_name(dev->of_node, "mcu-timing");
 	if (!mcu) {
@@ -5365,6 +5408,12 @@ static void vop_unbind(struct device *dev, struct device *master, void *data)
 {
 	struct vop *vop = dev_get_drvdata(dev);

+	if (vop->genpd_dev1)
+		dev_pm_domain_detach(vop->genpd_dev1, true);
+
+	if (vop->genpd_dev0)
+		dev_pm_domain_detach(vop->genpd_dev0, true);
+
 	pm_runtime_disable(dev);
 	vop_destroy_crtc(vop);
 }
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -447,6 +447,11 @@ struct vop_intr {
 	struct vop_reg status;
 };

+struct vop_urgency {
+	u8 urgen_thl;
+	u8 urgen_thh;
+};
+
 struct vop_scl_extension {
 	struct vop_reg cbcr_vsd_mode;
 	struct vop_reg cbcr_vsu_mode;
@@ -979,6 +984,13 @@ struct vop2_video_port_regs {
 	struct vop_reg csc_offset1;
 	struct vop_reg csc_offset2;

+	/* axi urgency */
+	struct vop_reg axi0_port_urgency_en;
+	struct vop_reg axi1_port_urgency_en;
+	struct vop_reg post_urgency_en;
+	struct vop_reg post_urgency_thl;
+	struct vop_reg post_urgency_thh;
+
 	/* color bar */
 	struct vop_reg color_bar_en;
 	struct vop_reg color_bar_mode;
@@ -1182,6 +1194,7 @@ struct vop2_video_port_data {
 	const u8 win_dly;
 	const u8 pixel_rate;
 	const struct vop_intr *intr;
+	const struct vop_urgency *urgency;
 	const struct vop_hdr_table *hdr_table;
 	const struct vop2_video_port_regs *regs;
 	const struct vop3_ovl_regs *ovl_regs;
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -1657,7 +1657,7 @@ static inline void rk3568_vop2_cfg_done(struct drm_crtc *crtc)
 	 */
 	val |= vop2_readl(vop2, RK3568_REG_CFG_DONE) & 0x7;

-	rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
+	rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n\n", val);

 	vop2_writel(vop2, 0, val);

@@ -1684,7 +1684,7 @@ static inline void rk3588_vop2_cfg_done(struct drm_crtc *crtc)
 	if (vcstate->splice_mode)
 		val |= BIT(vp_data->splice_vp_id) | (BIT(vp_data->splice_vp_id) << 16);

-	rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
+	rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n\n", val);

 	vop2_writel(vop2, 0, val);
 }
@@ -5803,11 +5803,12 @@ static void vop2_win_atomic_update(struct vop2_win *win, struct drm_rect *src, s
 	vop2_win_enable(win);
 	spin_lock(&vop2->reg_lock);
 	rockchip_drm_dbg(vop2->dev, VOP_DEBUG_PLANE,
-			 "vp%d update %s[%dx%d->%dx%d@(%d, %d)] fmt[%p4cc%s] addr[%pad] by %s\n",
-			 vp->id, win->name, actual_w, actual_h, dsp_w, dsp_h,
-			 dsp_stx, dsp_sty,
-			 &fb->format->format,
-			 modifier_to_string(fb->modifier), &vpstate->yrgb_mst, current->comm);
+			 "vp%d update %s[%dx%d@(%d, %d)->%dx%d@(%d, %d)] zpos[%d] fmt[%p4cc%s] addr[%pad] fb_size[0x%zx] by %s\n",
+			 vp->id, win->name,
+			 actual_w, actual_h, src->x1 >> 16, src->y1 >> 16,
+			 dsp_w, dsp_h, dsp_stx, dsp_sty, vpstate->zpos,
+			 &fb->format->format, modifier_to_string(fb->modifier),
+			 &vpstate->yrgb_mst, vpstate->fb_size, current->comm);

 	if (vop2->version != VOP_VERSION_RK3568)
 		rk3588_vop2_win_cfg_axi(win);
@@ -6063,13 +6064,17 @@ static void vop2_plane_atomic_update(struct drm_plane *plane, struct drm_atomic_
 	}

 	if (vcstate->splice_mode) {
-		DRM_DEV_DEBUG(vop2->dev, "vp%d update %s[%dx%d->%dx%d@(%d,%d)] fmt[%p4cc%s] addr[%pad]\n",
-			      vp->id, win->name, drm_rect_width(&vpstate->src) >> 16,
-			      drm_rect_height(&vpstate->src) >> 16,
-			      drm_rect_width(&vpstate->dest), drm_rect_height(&vpstate->dest),
-			      vpstate->dest.x1, vpstate->dest.y1,
-			      &fb->format->format,
-			      modifier_to_string(fb->modifier), &vpstate->yrgb_mst);
+		rockchip_drm_dbg(vop2->dev, VOP_DEBUG_PLANE,
+				 "vp%d update %s[%dx%d@(%d, %d)->%dx%d@(%d, %d)] zpos[%d] fmt[%p4cc%s] addr[%pad] fb_size[0x%zx] by %s\n",
+				 vp->id, win->name,
+				 drm_rect_width(&vpstate->src) >> 16,
+				 drm_rect_height(&vpstate->src) >> 16,
+				 vpstate->src.x1 >> 16, vpstate->src.y1 >> 16,
+				 drm_rect_width(&vpstate->dest), drm_rect_height(&vpstate->dest),
+				 vpstate->dest.x1, vpstate->dest.y1, vpstate->zpos,
+				 &fb->format->format,
+				 modifier_to_string(fb->modifier), &vpstate->yrgb_mst,
+				 vpstate->fb_size, current->comm);

 		vop2_calc_drm_rect_for_splice(vpstate, &wsrc, &wdst, &right_wsrc, &right_wdst);
 		splice_win = win->splice_win;
@@ -7224,6 +7229,10 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK || vcstate->output_if & VOP_OUTPUT_IF_BT656)
 		request_clock *= 2;

+	/* Pixel rate verify */
+	if (request_clock > vp_data->dclk_max / 1000)
+		return MODE_CLOCK_HIGH;
+
 	if ((request_clock <= VOP2_MAX_DCLK_RATE) &&
 	    (vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll") ||
 	     vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll"))) {
@@ -7239,9 +7248,6 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
 						     request_clock * 1000) / 1000;
 	}

-	if (request_clock > vp_data->dclk_max / 1000)
-		return MODE_CLOCK_HIGH;
-
 	/*
 	 * Hdmi or DisplayPort request a Accurate clock.
 	 */
@@ -8990,6 +8996,16 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_sta

 	VOP_MODULE_SET(vop2, vp, almost_full_or_en, 1);
 	VOP_MODULE_SET(vop2, vp, line_flag_or_en, 1);
+	if (vop2->data->vp[vp->id].urgency) {
+		u8 urgen_thl = vop2->data->vp[vp->id].urgency->urgen_thl;
+		u8 urgen_thh = vop2->data->vp[vp->id].urgency->urgen_thh;
+
+		VOP_MODULE_SET(vop2, vp, axi0_port_urgency_en, 1);
+		VOP_MODULE_SET(vop2, vp, axi1_port_urgency_en, 1);
+		VOP_MODULE_SET(vop2, vp, post_urgency_en, 1);
+		VOP_MODULE_SET(vop2, vp, post_urgency_thl, urgen_thl);
+		VOP_MODULE_SET(vop2, vp, post_urgency_thh, urgen_thh);
+	}
 	if (vcstate->dsc_enable) {
 		if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
 			vop2_crtc_enable_dsc(crtc, old_cstate, 0);
@@ -12491,7 +12507,7 @@ static int vop2_crtc_create_feature_property(struct vop2 *vop2, struct drm_crtc
 	drm_object_attach_property(&crtc->base, vp->output_width_prop, 0);

 	prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE, "OUTPUT_DCLK",
-					 0, rockchip_drm_get_dclk_by_width(vop2->data->vp[vp->id].max_output.width) * 1000);
+					 0, vop2->data->vp[vp->id].dclk_max);
 	if (!prop) {
 		DRM_DEV_ERROR(vop2->dev, "create OUTPUT_DCLK prop for vp%d failed\n", vp->id);
 		return -ENOMEM;
--- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
@@ -1577,6 +1577,11 @@ static const struct vop2_video_port_regs rk3576_vop_vp0_regs = {

 	.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 20),
 	.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 28),
+	.axi0_port_urgency_en = VOP_REG(RK3576_SYS_AXI_HURRY_CTRL0_IMD, 0x1, 24),
+	.axi1_port_urgency_en = VOP_REG(RK3576_SYS_AXI_HURRY_CTRL1_IMD, 0x1, 24),
+	.post_urgency_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 8),
+	.post_urgency_thl = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0xf, 16),
+	.post_urgency_thh = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0xf, 20),
 };

 static const struct vop2_video_port_regs rk3576_vop_vp1_regs = {
@@ -1652,6 +1657,11 @@ static const struct vop2_video_port_regs rk3576_vop_vp1_regs = {

 	.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 21),
 	.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 29),
+	.axi0_port_urgency_en = VOP_REG(RK3576_SYS_AXI_HURRY_CTRL0_IMD, 0x1, 25),
+	.axi1_port_urgency_en = VOP_REG(RK3576_SYS_AXI_HURRY_CTRL1_IMD, 0x1, 25),
+	.post_urgency_en = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 8),
+	.post_urgency_thl = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0xf, 16),
+	.post_urgency_thh = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0xf, 20),
 };

 static const struct vop2_video_port_regs rk3576_vop_vp2_regs = {
@@ -1727,6 +1737,11 @@ static const struct vop2_video_port_regs rk3576_vop_vp2_regs = {

 	.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 22),
 	.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 30),
+	.axi0_port_urgency_en = VOP_REG(RK3576_SYS_AXI_HURRY_CTRL0_IMD, 0x1, 26),
+	.axi1_port_urgency_en = VOP_REG(RK3576_SYS_AXI_HURRY_CTRL1_IMD, 0x1, 26),
+	.post_urgency_en = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 8),
+	.post_urgency_thl = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0xf, 16),
+	.post_urgency_thh = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0xf, 20),
 };

 static const struct vop3_ovl_regs rk3576_vop_vp0_ovl_regs = {
@@ -1735,6 +1750,16 @@ static const struct vop3_ovl_regs rk3576_vop_vp0_ovl_regs = {
 	 .extra_mix_regs = &rk3576_vop_extra_mix_regs,
 };

+/*
+ * RK3576 VP0 has 8 lines post linebuffer, when full post line buffer is less 4,
+ * the urgency signal will be set to 1, when full post line buffer is over 6, the
+ * urgency signal will be set to 0.
+ */
+static const struct vop_urgency rk3576_vp0_urgency = {
+	.urgen_thl = 4,
+	.urgen_thh = 6,
+};
+
 static const struct vop2_video_port_data rk3576_vop_video_ports[] = {
 	{
 	 .id = 0,
@@ -1745,7 +1770,7 @@ static const struct vop2_video_port_data rk3576_vop_video_ports[] = {
 			VOP_FEATURE_POST_FRC_V2 | VOP_FEATURE_POST_SHARP,
 	 .gamma_lut_len = 1024,
 	 .cubic_lut_len = 729, /* 9x9x9 */
-	 .dclk_max = 600000000,
+	 .dclk_max = 1200000000,
 	 .max_output = { 4096, 4096 },
 	 .hdrvivid_dly = {17, 29, 32, 44, 15, 38, 1, 29, 0, 0},
 	 .sdr2hdr_dly = 21,
@@ -1754,6 +1779,7 @@ static const struct vop2_video_port_data rk3576_vop_video_ports[] = {
 	 .win_dly = 10,
 	 .pixel_rate = 2,
 	 .intr = &rk3568_vp0_intr,
+	 .urgency = &rk3576_vp0_urgency,
 	 .regs = &rk3576_vop_vp0_regs,
 	 .ovl_regs = &rk3576_vop_vp0_ovl_regs,
 	},
@@ -2134,7 +2160,7 @@ static const struct vop2_video_port_data rk3588_vop_video_ports[] = {
 			VOP_FEATURE_HDR10 | VOP_FEATURE_NEXT_HDR,
 	 .gamma_lut_len = 1024,
 	 .cubic_lut_len = 729, /* 9x9x9 */
-	 .dclk_max = 600000000,
+	 .dclk_max = 2400000000,
 	 .max_output = { 7680, 4320 },
 	 /* hdr2sdr sdr2hdr hdr2hdr sdr2sdr */
 	 .pre_scan_max_dly = { 76, 65, 65, 54 },
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
@@ -1050,6 +1050,8 @@
 #define RK3568_VOP2_GLB_CFG_DONE_EN		BIT(15)
 #define RK3568_VERSION_INFO			0x004
 #define RK3568_SYS_AUTO_GATING_CTRL		0x008
+#define RK3576_SYS_AXI_HURRY_CTRL0_IMD		0x014
+#define RK3576_SYS_AXI_HURRY_CTRL1_IMD		0x018
 #define RK3576_SYS_MMU_CTRL_IMD			0x020
 #define RK3568_SYS_AXI_LUT_CTRL			0x024
 #define RK3568_DSP_IF_EN			0x028
--- a/drivers/media/i2c/rk628/rk628_csi_v4l2.c
+++ b/drivers/media/i2c/rk628/rk628_csi_v4l2.c
@@ -2359,10 +2359,12 @@ static int mipi_dphy_power_on(struct rk628_csi *csi)
 		rk628_mipi_dphy_init_hsmanual(csi->rk628, true, 1);
 	} else if (csi->lane_mbps == MIPI_DATARATE_MBPS_HIGH && !csi->rk628->dual_mipi) {
 		rk628_mipi_dphy_init_hsmanual(csi->rk628, true, 0);
-		rk628_mipi_dphy_init_hsmanual(csi->rk628, false, 1);
+		if (csi->rk628->version >= RK628F_VERSION)
+			rk628_mipi_dphy_init_hsmanual(csi->rk628, false, 1);
 	} else {
 		rk628_mipi_dphy_init_hsmanual(csi->rk628, false, 0);
-		rk628_mipi_dphy_init_hsmanual(csi->rk628, false, 1);
+		if (csi->rk628->version >= RK628F_VERSION)
+			rk628_mipi_dphy_init_hsmanual(csi->rk628, false, 1);
 	}

 	usleep_range(1500, 2000);
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -496,7 +496,7 @@ static const struct dwcmshc_driver_data dwcmshc_drvdata = {

 static const struct dwcmshc_driver_data rk3568_drvdata = {
 	.pdata = &sdhci_dwcmshc_rk35xx_pdata,
-	.flags = RK_PLATFROM | RK_RXCLK_NO_INVERTER,
+	.flags = RK_PLATFROM | RK_RXCLK_NO_INVERTER | RK_TAP_VALUE_SEL,
 	.hs200_tx_tap = 16,
 	.hs400_tx_tap = 8,
 	.hs400_cmd_tap = 8,
@@ -506,7 +506,7 @@ static const struct dwcmshc_driver_data rk3568_drvdata = {

 static const struct dwcmshc_driver_data rk3588_drvdata = {
 	.pdata = &sdhci_dwcmshc_rk35xx_pdata,
-	.flags = RK_PLATFROM | RK_DLL_CMD_OUT,
+	.flags = RK_PLATFROM | RK_DLL_CMD_OUT | RK_TAP_VALUE_SEL,
 	.hs200_tx_tap = 16,
 	.hs400_tx_tap = 9,
 	.hs400_cmd_tap = 8,
--- a/drivers/power/supply/rockchip_charger_manager.c
+++ b/drivers/power/supply/rockchip_charger_manager.c
@@ -2340,6 +2340,10 @@ static int cm_pps_adapter_det(struct charger_manager *cm)
 			queue_delayed_work(cm->cm_wq, &cm->cm_monitor_work, 300);
 		cm->fc_charger_enabled = 1;
 	} else {
+		if (cm->fc_config->jeita_charge_support) {
+			cancel_delayed_work(&cm->cm_jeita_work);
+			queue_delayed_work(cm->cm_wq, &cm->cm_jeita_work, 1000);
+		}
 		val.intval = 1;
 		ret = power_supply_set_property(cm->desc->tcpm_psy,
 						POWER_SUPPLY_PROP_ONLINE,
--- a/drivers/regulator/rk806-regulator.c
+++ b/drivers/regulator/rk806-regulator.c
@@ -681,7 +681,9 @@ static int rk806_regulator_resume(struct regulator_dev *rdev)
 static int rk806_set_suspend_voltage_range(struct regulator_dev *rdev, int uv)
 {
 	struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
-	int sel = regulator_map_voltage_linear_range(rdev, uv, uv);
+	int sel = regulator_map_voltage_linear_range(rdev,
+						     uv,
+						     rdev->constraints->max_uV);
 	struct rk806 *rk806 = pdata->rk806;
 	int rid = rdev_get_id(rdev);
 	int reg_offset;
@@ -725,6 +727,8 @@ static int rk806_set_voltage(struct regulator_dev *rdev,
 	int ret;
 	int sel;

+	if (req_min_uV == req_max_uV)
+		req_max_uV = rdev->constraints->max_uV;
 	ret = regulator_map_voltage_linear_range(rdev, req_min_uV, req_max_uV);
 	if (ret >= 0) {
 		*selector = ret;
@@ -1165,8 +1169,6 @@ static int __maybe_unused rk806_suspend(struct device *dev)
 	int i;

 	rk806_field_write(rk806, PWRCTRL1_FUN, PWRCTRL_NULL_FUN);
-	rk806_field_write(rk806, PWRCTRL2_FUN, PWRCTRL_NULL_FUN);
-	rk806_field_write(rk806, PWRCTRL3_FUN, PWRCTRL_NULL_FUN);

 	for (i = RK806_ID_DCDC1; i < RK806_ID_END; i++)
 		rk806_field_write(rk806, BUCK1_VSEL_CTR_SEL + i, CTR_BY_NO_EFFECT);