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BACKPORT: dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY

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Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
Processing System Gigabit Transceiver which provides PHY capabilities to
USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.

Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
(cherry picked from commit cea0f76a48)

Change-Id: I1d4d304350ad1d48ce369411110d20c30d7f2a9c
Signed-off-by: David Wu <david.wu@rock-chips.com>
This commit is contained in:
Anurag Kumar Vulisha
2020-06-29 15:00:52 +03:00
committed by Tao Huang
parent d0a93df32c
commit 72d00ccae5
1 changed files with 1 additions and 0 deletions
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include/dt-bindings/phy/phy.h
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@@ -18,5 +18,6 @@
#define PHY_TYPE_UFS 5
#define PHY_TYPE_DP 6
#define PHY_TYPE_XPCS 7
#define PHY_TYPE_SGMII 8
#endif /* _DT_BINDINGS_PHY */