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clk: rockchip: rk1808: remove the apll from parents clk for npu

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apll is always change,
not allowed apll as npu parent clk.

Change-Id: Ia354b7ac533c2c7537d2d25894f956b855db9bc6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2018-10-19 16:03:06 +08:00
committed by Tao Huang
parent 4202ab5440
commit 7393188064
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk1808.c
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@@ -334,9 +334,9 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = {
/*
* Clock-Architecture Diagram 4
*/
COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_apll_p, 0,
COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_p, CLK_KEEP_REQ_RATE,
RK1808_CLKSEL_CON(1), 8, 2, MFLAGS, 0, 4, DFLAGS),
COMPOSITE_NOGATE_HALFDIV(0, "clk_npu_np5", mux_gpll_cpll_apll_p, 0,
COMPOSITE_NOGATE_HALFDIV(0, "clk_npu_np5", mux_gpll_cpll_p, CLK_KEEP_REQ_RATE,
RK1808_CLKSEL_CON(1), 10, 2, MFLAGS, 4, 4, DFLAGS),
MUX(0, "clk_npu_pre", mux_npu_p, CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(1), 15, 1, MFLAGS),