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ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees

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Add OPP tables and power domains to all peripheral devices which
support power management on Tegra30 SoC.

Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko
2021-12-01 02:23:44 +03:00
committed by Thierry Reding
parent 83b7f0b8ae
commit 73e2b72a35
7 changed files with 1395 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
View File

@@ -968,6 +968,7 @@
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
ahub@70080000 {

1
arch/arm/boot/dts/tegra30-beaver.dts
View File

@@ -1916,6 +1916,7 @@
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
core-supply = <&core_vdd_reg>;
};
ahub@70080000 {

1
arch/arm/boot/dts/tegra30-cardhu.dtsi
View File

@@ -393,6 +393,7 @@
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
ahub@70080000 {

17
arch/arm/boot/dts/tegra30-colibri.dtsi
View File

@@ -767,9 +767,14 @@
vddctrl_reg: vddctrl {
regulator-name = "+V1.0_VDD_CPU";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
regulator-coupled-with = <&vdd_core>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
regulator-always-on;
nvidia,tegra-cpu-regulator;
};
reg_1v8_vio: vio {
@@ -892,15 +897,20 @@
};
/* SW: +V1.2_VDD_CORE */
regulator@60 {
vdd_core: regulator@60 {
compatible = "ti,tps62362";
reg = <0x60>;
regulator-name = "tps62362-vout";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1400000>;
regulator-coupled-with = <&vddctrl_reg>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
regulator-boot-on;
regulator-always-on;
nvidia,tegra-core-regulator;
};
};
@@ -913,6 +923,7 @@
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
/* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
i2c-thermtrip {

1
arch/arm/boot/dts/tegra30-ouya.dts
View File

@@ -2195,6 +2195,7 @@
nvidia,core-pwr-off-time = <458>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
memory-controller@7000f000 {

1224
arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
View File

File diff suppressed because it is too large Load Diff

153
arch/arm/boot/dts/tegra30.dtsi
View File

@@ -55,6 +55,8 @@
<&tegra_car 72>,
<&tegra_car 74>;
reset-names = "pex", "afi", "pcie_x";
power-domains = <&pd_core>;
operating-points-v2 = <&pcie_dvfs_opp_table>;
status = "disabled";
pci@1,0 {
@@ -124,6 +126,8 @@
resets = <&tegra_car 28>;
reset-names = "host1x";
iommus = <&mc TEGRA_SWGROUP_HC>;
power-domains = <&pd_heg>;
operating-points-v2 = <&host1x_dvfs_opp_table>;
#address-cells = <1>;
#size-cells = <1>;
@@ -137,6 +141,8 @@
clocks = <&tegra_car TEGRA30_CLK_MPE>;
resets = <&tegra_car 60>;
reset-names = "mpe";
power-domains = <&pd_mpe>;
operating-points-v2 = <&mpe_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_MPE>;
};
@@ -148,6 +154,8 @@
clocks = <&tegra_car TEGRA30_CLK_VI>;
resets = <&tegra_car 20>;
reset-names = "vi";
power-domains = <&pd_venc>;
operating-points-v2 = <&vi_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_VI>;
};
@@ -159,6 +167,8 @@
clocks = <&tegra_car TEGRA30_CLK_EPP>;
resets = <&tegra_car 19>;
reset-names = "epp";
power-domains = <&pd_heg>;
operating-points-v2 = <&epp_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_EPP>;
};
@@ -170,6 +180,7 @@
clocks = <&tegra_car TEGRA30_CLK_ISP>;
resets = <&tegra_car 23>;
reset-names = "isp";
power-domains = <&pd_venc>;
iommus = <&mc TEGRA_SWGROUP_ISP>;
};
@@ -181,6 +192,8 @@
clocks = <&tegra_car TEGRA30_CLK_GR2D>;
resets = <&tegra_car 21>;
reset-names = "2d";
power-domains = <&pd_heg>;
operating-points-v2 = <&gr2d_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_G2>;
};
@@ -194,6 +207,9 @@
resets = <&tegra_car 24>,
<&tegra_car 98>;
reset-names = "3d", "3d2";
power-domains = <&pd_3d0>, <&pd_3d1>;
power-domain-names = "3d0", "3d1";
operating-points-v2 = <&gr3d_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_NV>,
<&mc TEGRA_SWGROUP_NV2>;
@@ -208,6 +224,8 @@
clock-names = "dc", "parent";
resets = <&tegra_car 27>;
reset-names = "dc";
power-domains = <&pd_core>;
operating-points-v2 = <&disp1_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_DC>;
@@ -238,6 +256,8 @@
clock-names = "dc", "parent";
resets = <&tegra_car 26>;
reset-names = "dc";
power-domains = <&pd_core>;
operating-points-v2 = <&disp2_dvfs_opp_table>;
iommus = <&mc TEGRA_SWGROUP_DCB>;
@@ -268,6 +288,8 @@
clock-names = "hdmi", "parent";
resets = <&tegra_car 51>;
reset-names = "hdmi";
power-domains = <&pd_core>;
operating-points-v2 = <&hdmi_dvfs_opp_table>;
status = "disabled";
};
@@ -276,6 +298,8 @@
reg = <0x542c0000 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_TVO>;
power-domains = <&pd_core>;
operating-points-v2 = <&tvo_dvfs_opp_table>;
status = "disabled";
};
@@ -287,6 +311,8 @@
clock-names = "dsi", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
power-domains = <&pd_core>;
operating-points-v2 = <&dsia_dvfs_opp_table>;
status = "disabled";
};
@@ -298,6 +324,8 @@
clock-names = "dsi", "parent";
resets = <&tegra_car 84>;
reset-names = "dsi";
power-domains = <&pd_core>;
operating-points-v2 = <&dsib_dvfs_opp_table>;
status = "disabled";
};
};
@@ -358,6 +386,34 @@
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
sclk {
compatible = "nvidia,tegra30-sclk";
clocks = <&tegra_car TEGRA30_CLK_SCLK>;
power-domains = <&pd_core>;
operating-points-v2 = <&sclk_dvfs_opp_table>;
};
pll-c {
compatible = "nvidia,tegra30-pllc";
clocks = <&tegra_car TEGRA30_CLK_PLL_C>;
power-domains = <&pd_core>;
operating-points-v2 = <&pll_c_dvfs_opp_table>;
};
pll-e {
compatible = "nvidia,tegra30-plle";
clocks = <&tegra_car TEGRA30_CLK_PLL_E>;
power-domains = <&pd_core>;
operating-points-v2 = <&pll_e_dvfs_opp_table>;
};
pll-m {
compatible = "nvidia,tegra30-pllm";
clocks = <&tegra_car TEGRA30_CLK_PLL_M>;
power-domains = <&pd_core>;
operating-points-v2 = <&pll_m_dvfs_opp_table>;
};
};
flow-controller@60007000 {
@@ -468,6 +524,8 @@
reset-names = "vde", "mc";
resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
iommus = <&mc TEGRA_SWGROUP_VDE>;
power-domains = <&pd_vde>;
operating-points-v2 = <&vde_dvfs_opp_table>;
};
apbmisc@70000800 {
@@ -565,6 +623,8 @@
clock-names = "gmi";
resets = <&tegra_car 42>;
reset-names = "gmi";
power-domains = <&pd_core>;
operating-points-v2 = <&nor_dvfs_opp_table>;
status = "disabled";
};
@@ -575,6 +635,8 @@
clocks = <&tegra_car TEGRA30_CLK_PWM>;
resets = <&tegra_car 17>;
reset-names = "pwm";
power-domains = <&pd_core>;
operating-points-v2 = <&pwm_dvfs_opp_table>;
status = "disabled";
};
@@ -676,6 +738,8 @@
reset-names = "spi";
dmas = <&apbdma 15>, <&apbdma 15>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
operating-points-v2 = <&sbc1_dvfs_opp_table>;
status = "disabled";
};
@@ -690,6 +754,8 @@
reset-names = "spi";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
operating-points-v2 = <&sbc2_dvfs_opp_table>;
status = "disabled";
};
@@ -704,6 +770,8 @@
reset-names = "spi";
dmas = <&apbdma 17>, <&apbdma 17>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
operating-points-v2 = <&sbc3_dvfs_opp_table>;
status = "disabled";
};
@@ -718,6 +786,8 @@
reset-names = "spi";
dmas = <&apbdma 18>, <&apbdma 18>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
operating-points-v2 = <&sbc4_dvfs_opp_table>;
status = "disabled";
};
@@ -732,6 +802,8 @@
reset-names = "spi";
dmas = <&apbdma 27>, <&apbdma 27>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
operating-points-v2 = <&sbc5_dvfs_opp_table>;
status = "disabled";
};
@@ -746,6 +818,8 @@
reset-names = "spi";
dmas = <&apbdma 28>, <&apbdma 28>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
operating-points-v2 = <&sbc6_dvfs_opp_table>;
status = "disabled";
};
@@ -765,6 +839,72 @@
clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
#clock-cells = <1>;
pd_core: core-domain {
#power-domain-cells = <0>;
operating-points-v2 = <&core_opp_table>;
};
powergates {
pd_3d0: td {
clocks = <&tegra_car TEGRA30_CLK_GR3D>;
resets = <&mc TEGRA30_MC_RESET_3D>,
<&tegra_car TEGRA30_CLK_GR3D>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_3d1: td2 {
clocks = <&tegra_car TEGRA30_CLK_GR3D2>;
resets = <&mc TEGRA30_MC_RESET_3D2>,
<&tegra_car TEGRA30_CLK_GR3D2>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_venc: venc {
clocks = <&tegra_car TEGRA30_CLK_ISP>,
<&tegra_car TEGRA30_CLK_VI>,
<&tegra_car TEGRA30_CLK_CSI>;
resets = <&mc TEGRA30_MC_RESET_ISP>,
<&mc TEGRA30_MC_RESET_VI>,
<&tegra_car TEGRA30_CLK_ISP>,
<&tegra_car 20 /* VI */>,
<&tegra_car TEGRA30_CLK_CSI>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_vde: vdec {
clocks = <&tegra_car TEGRA30_CLK_VDE>;
resets = <&mc TEGRA30_MC_RESET_VDE>,
<&tegra_car TEGRA30_CLK_VDE>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_mpe: mpe {
clocks = <&tegra_car TEGRA30_CLK_MPE>;
resets = <&mc TEGRA30_MC_RESET_MPE>,
<&tegra_car TEGRA30_CLK_MPE>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_heg: heg {
clocks = <&tegra_car TEGRA30_CLK_GR2D>,
<&tegra_car TEGRA30_CLK_EPP>,
<&tegra_car TEGRA30_CLK_HOST1X>;
resets = <&mc TEGRA30_MC_RESET_2D>,
<&mc TEGRA30_MC_RESET_EPP>,
<&mc TEGRA30_MC_RESET_HC>,
<&tegra_car TEGRA30_CLK_GR2D>,
<&tegra_car TEGRA30_CLK_EPP>,
<&tegra_car TEGRA30_CLK_HOST1X>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
};
};
mc: memory-controller@7000f000 {
@@ -785,6 +925,7 @@
reg = <0x7000f400 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_EMC>;
power-domains = <&pd_core>;
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&emc_icc_dvfs_opp_table>;
@@ -799,6 +940,8 @@
clock-names = "fuse";
resets = <&tegra_car 39>;
reset-names = "fuse";
power-domains = <&pd_core>;
operating-points-v2 = <&fuse_burn_dvfs_opp_table>;
};
tsensor: tsensor@70014000 {
@@ -921,6 +1064,8 @@
clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
power-domains = <&pd_core>;
operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
status = "disabled";
};
@@ -943,6 +1088,8 @@
clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
power-domains = <&pd_core>;
operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
status = "disabled";
};
@@ -967,6 +1114,8 @@
reset-names = "usb";
nvidia,needs-double-reset;
nvidia,phy = <&phy1>;
power-domains = <&pd_core>;
operating-points-v2 = <&usbd_dvfs_opp_table>;
status = "disabled";
};
@@ -1008,6 +1157,8 @@
resets = <&tegra_car 58>;
reset-names = "usb";
nvidia,phy = <&phy2>;
power-domains = <&pd_core>;
operating-points-v2 = <&usb2_dvfs_opp_table>;
status = "disabled";
};
@@ -1048,6 +1199,8 @@
resets = <&tegra_car 59>;
reset-names = "usb";
nvidia,phy = <&phy3>;
power-domains = <&pd_core>;
operating-points-v2 = <&usb3_dvfs_opp_table>;
status = "disabled";
};