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ARM: rockchip: cpu_axi support extcontrol

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黄涛
2014-03-25 19:12:44 +08:00
parent 03317364ff
commit 7425dd7c4f
2 changed files with 22 additions and 22 deletions
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36
arch/arm/mach-rockchip/common.c
View File

@@ -37,10 +37,12 @@ static int __init rockchip_cpu_axi_init(void)
if (!np)
return -ENODEV;
#define MAP(base) if (!base) base = of_iomap(cp, 0); if (!base) continue;
gp = of_get_child_by_name(np, "qos");
if (gp) {
for_each_child_of_node(gp, cp) {
u32 priority[2], mode, bandwidth, saturation;
u32 priority[2], mode, bandwidth, saturation, extcontrol;
base = NULL;
#ifdef DEBUG
{
@@ -50,37 +52,30 @@ static int __init rockchip_cpu_axi_init(void)
}
#endif
if (!of_property_read_u32_array(cp, "rockchip,priority", priority, ARRAY_SIZE(priority))) {
if (!base)
base = of_iomap(cp, 0);
if (!base)
continue;
MAP(base);
CPU_AXI_SET_QOS_PRIORITY(priority[0], priority[1], base);
pr_debug("qos: %s priority %x %x\n", cp->name, priority[0], priority[1]);
}
if (!of_property_read_u32(cp, "rockchip,mode", &mode)) {
if (!base)
base = of_iomap(cp, 0);
if (!base)
continue;
MAP(base);
CPU_AXI_SET_QOS_MODE(mode, base);
pr_debug("qos: %s mode %x\n", cp->name, mode);
}
if (!of_property_read_u32(cp, "rockchip,bandwidth", &bandwidth)) {
if (!base)
base = of_iomap(cp, 0);
if (!base)
continue;
MAP(base);
CPU_AXI_SET_QOS_BANDWIDTH(bandwidth, base);
pr_debug("qos: %s bandwidth %x\n", cp->name, bandwidth);
}
if (!of_property_read_u32(cp, "rockchip,saturation", &saturation)) {
if (!base)
base = of_iomap(cp, 0);
if (!base)
continue;
MAP(base);
CPU_AXI_SET_QOS_SATURATION(saturation, base);
pr_debug("qos: %s saturation %x\n", cp->name, saturation);
}
if (!of_property_read_u32(cp, "rockchip,extcontrol", &extcontrol)) {
MAP(base);
CPU_AXI_SET_QOS_EXTCONTROL(extcontrol, base);
pr_debug("qos: %s extcontrol %x\n", cp->name, extcontrol);
}
if (base)
iounmap(base);
}
@@ -99,10 +94,7 @@ static int __init rockchip_cpu_axi_init(void)
}
#endif
if (!of_property_read_u32(cp, "rockchip,read-latency", &val)) {
if (!base)
base = of_iomap(cp, 0);
if (!base)
continue;
MAP(base);
writel_relaxed(val, base + 0x0014); // memory scheduler read latency
pr_debug("msch: %s read latency %x\n", cp->name, val);
}
@@ -112,6 +104,8 @@ static int __init rockchip_cpu_axi_init(void)
}
dsb();
#undef MAP
return 0;
}
early_initcall(rockchip_cpu_axi_init);

8
arch/arm/mach-rockchip/cpu_axi.h
View File

@@ -5,6 +5,7 @@
#define CPU_AXI_QOS_MODE 0x0c
#define CPU_AXI_QOS_BANDWIDTH 0x10
#define CPU_AXI_QOS_SATURATION 0x14
#define CPU_AXI_QOS_EXTCONTROL 0x18
#define CPU_AXI_QOS_MODE_NONE 0
#define CPU_AXI_QOS_MODE_FIXED 1
@@ -24,18 +25,23 @@
#define CPU_AXI_SET_QOS_SATURATION(saturation, base) \
writel_relaxed((saturation) & 0x3ff, base + CPU_AXI_QOS_SATURATION)
#define CPU_AXI_QOS_NUM_REGS 4
#define CPU_AXI_SET_QOS_EXTCONTROL(extcontrol, base) \
writel_relaxed((extcontrol) & 7, base + CPU_AXI_QOS_EXTCONTROL)
#define CPU_AXI_QOS_NUM_REGS 5
#define CPU_AXI_SAVE_QOS(array, base) do { \
array[0] = readl_relaxed(base + CPU_AXI_QOS_PRIORITY); \
array[1] = readl_relaxed(base + CPU_AXI_QOS_MODE); \
array[2] = readl_relaxed(base + CPU_AXI_QOS_BANDWIDTH); \
array[3] = readl_relaxed(base + CPU_AXI_QOS_SATURATION); \
array[4] = readl_relaxed(base + CPU_AXI_QOS_EXTCONTROL); \
} while (0)
#define CPU_AXI_RESTORE_QOS(array, base) do { \
writel_relaxed(array[0], base + CPU_AXI_QOS_PRIORITY); \
writel_relaxed(array[1], base + CPU_AXI_QOS_MODE); \
writel_relaxed(array[2], base + CPU_AXI_QOS_BANDWIDTH); \
writel_relaxed(array[3], base + CPU_AXI_QOS_SATURATION); \
writel_relaxed(array[4], base + CPU_AXI_QOS_EXTCONTROL); \
} while (0)
#define RK3188_CPU_AXI_DMAC_QOS_VIRT (RK_CPU_AXI_BUS_VIRT + 0x1000)