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drm/rockchip: vop2: use pixel rate to verify vp performance

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get vp max dclk rate from vop reg data is more correct, so we use it to
verify vp performance and report to userspace.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I1e590322829e551814ba84bf22d60a4e82b407d1
This commit is contained in:
Sandy Huang
2024-03-29 15:56:01 +08:00
parent 5a55616dcf
commit 742e1e510b
2 changed files with 7 additions and 6 deletions
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9
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -7229,6 +7229,10 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
if (mode->flags & DRM_MODE_FLAG_DBLCLK || vcstate->output_if & VOP_OUTPUT_IF_BT656)
request_clock *= 2;
/* Pixel rate verify */
if (request_clock > vp_data->dclk_max / 1000)
return MODE_CLOCK_HIGH;
if ((request_clock <= VOP2_MAX_DCLK_RATE) &&
(vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll") ||
vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll"))) {
@@ -7244,9 +7248,6 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
request_clock * 1000) / 1000;
}
if (request_clock > vp_data->dclk_max / 1000)
return MODE_CLOCK_HIGH;
/*
* Hdmi or DisplayPort request a Accurate clock.
*/
@@ -12496,7 +12497,7 @@ static int vop2_crtc_create_feature_property(struct vop2 *vop2, struct drm_crtc
drm_object_attach_property(&crtc->base, vp->output_width_prop, 0);
prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE, "OUTPUT_DCLK",
0, rockchip_drm_get_dclk_by_width(vop2->data->vp[vp->id].max_output.width) * 1000);
0, vop2->data->vp[vp->id].dclk_max);
if (!prop) {
DRM_DEV_ERROR(vop2->dev, "create OUTPUT_DCLK prop for vp%d failed\n", vp->id);
return -ENOMEM;

4
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -1745,7 +1745,7 @@ static const struct vop2_video_port_data rk3576_vop_video_ports[] = {
VOP_FEATURE_POST_FRC_V2 | VOP_FEATURE_POST_SHARP,
.gamma_lut_len = 1024,
.cubic_lut_len = 729, /* 9x9x9 */
.dclk_max = 600000000,
.dclk_max = 1200000000,
.max_output = { 4096, 4096 },
.hdrvivid_dly = {17, 29, 32, 44, 15, 38, 1, 29, 0, 0},
.sdr2hdr_dly = 21,
@@ -2134,7 +2134,7 @@ static const struct vop2_video_port_data rk3588_vop_video_ports[] = {
VOP_FEATURE_HDR10 | VOP_FEATURE_NEXT_HDR,
.gamma_lut_len = 1024,
.cubic_lut_len = 729, /* 9x9x9 */
.dclk_max = 600000000,
.dclk_max = 2400000000,
.max_output = { 7680, 4320 },
/* hdr2sdr sdr2hdr hdr2hdr sdr2sdr */
.pre_scan_max_dly = { 76, 65, 65, 54 },